IS200DTAOH1ABA IS210DTAOH1AA燃机模块，GE使用尺寸

如果VMEbus主机正在执行读-修改-写循环（RMC）对于DRAM，GCC多端口仲裁器允许本地总线在读写部分之间重新比特序列。然而，它不允许MC68030重新获得本地总线主控，直到读写周期都DRAM发生。当VMEbus请求本地总线主控和MC68030时是当前本地总线主节点，它正在执行一个循环需要VMEbus，然后出现双端口锁定情况，并且VMEchip通过激活BERR*和HALT*信号线在一起。

IS200DTAOH1ABA IS210DTAOH1AA燃机模块MC68030通过以下方式响应：中止当前循环，此时放弃本地总线主控权，以便GCC多端口仲裁器可以将其授予VMEbus。当VMEbus完成DRAM时，GCC多端口仲裁器将本地总线主控权返回给MC68030和它重试已中止的循环以允许双端口访问。

LANCE DRAM访问当LANCE需要访问DRAM时，它请求本地总线GCC多端口仲裁器的主控权。获得批准后LANCE最多执行16次DRAM访问，然后放弃本地总线大师级。如果启用时发生奇偶校验错误，则DRAM控制器通过不激活LANRDY*到喷枪来指示。LANCE将此视为内存故障，并放弃本地总线Mastership刷新DRAM设备要求其4096/2048/1024行中的每一行每64/32/16毫秒刷新一次。为此，刷新计时器每15微秒请求一次RAM序列器执行列地址选通（CAS）之前行地址选通（RAS）刷新周期。

If the VMEbus master is executing a read-modify-write cycle

(RMC) to the DRAM, the GCC multiport arbiter allows rearbitration of the local bus between the read and write portions of

the sequence. It does not, however, allow the MC68030 to regain

local bus mastership until both the read and write cycles have

occurred to the DRAM.

When the VMEbus requests local bus mastership and the MC68030

is the current local bus master and it is executing a cycle that

requires the VMEbus, then a dual port lockup condition occurs and

the VMEchip signals a retry to the MC68030 by activating the

BERR* and HALT* signal lines together. The MC68030 responds by

aborting the current cycle, at which time it relinquishes local bus

mastership so that the GCC multiport arbiter can grant it to the

VMEbus. When the VMEbus has finished with the DRAM, the GCC

multiport arbiter returns local bus mastership to the MC68030 and

it retries the cycle that was aborted to allow the dual port access.

LANCE DRAM Accesses

When the LANCE needs to access DRAM it requests local bus

mastership from the GCC multiport arbiter. When granted, the

LANCE performs up to 16 DRAM accesses, then gives up local bus

mastership. If a parity error occurs while enabled, the DRAM

controller indicates it by not activating LANRDY* to the LANCE.

The LANCE sees this as a memory fault and gives up local bus

mastershipRefresh

The DRAM devices require that each of their 4096/2048/1024 rows

be refreshed once every 64/32/16 milliseconds. To accomplish this,

once every 15 microseconds, the refresh timer requests that the

RAM sequencer perform a Column Address Strobe (CAS) before

Row Address Strobe (RAS) refresh cycle.