IS200DTAIH1ACC IS210DTAOH1AA燃机模块，GE使用进展

DRAM可通过MC68030、PCC、LANCE和VMEbus。它专门针对MC68030进行了优化。MVME147-010上未实现奇偶校验功能。MVME147具有奇偶校验，在三个用户中的一个用户中运行可选模式。在模式1中，不执行奇偶校验，DRAM工作以最大速度。

在模式2中，对所有总线主机和当MC68030为总线时，DRAM以最大速度运行主人当模式2中出现奇偶校验错误且MC68030为在本地总线主控器中，总线错误信号在当前周期。

IS200DTAIH1ACC IS210DTAOH1AA燃机模块总线错误在所有后续事件中激活MC68030 DRAM周期。通知所有其他总线主控器奇偶校验当前周期中的错误，因此其DRAM访问时间增加1个时钟。在模式3中，对所有总线主机和在当前周期内报告奇偶校验错误。在这种模式下DRAM访问时间延长一个时钟周期，以允许奇偶校验检查。

MC68030 DRAM访问MC68030是默认的本地总线主机，因此它是本地总线总线主控，只要没有其他设备请求本地总线主控。PCC DRAM访问当PCC需要传输数据时，它请求本地总线GCC多端口仲裁器的主控权。当PCC被授予本地总线主控权后，它执行一个总线周期然后释放总线主控权。如果在测试过程中检测到奇偶校验错误PCC到DRAM的读取周期，总线错误返回到PCC。功能描述当VMEbus map解码器检测到车载DRAM选择时，VMEchip从GCC请求本地总线主控多端口仲裁器。当GCC多端口仲裁器已授予本地总线主控，发生DRAM读写循环，并且

VMEchip激活DTACK*（或BERR*，如果启用奇偶校验，并且VMEbus上出现奇偶校验错误）信号。

Onboard DRAM

The DRAM is accessible by the MC68030, PCC, LANCE, and

VMEbus. It is specifically optimized for the MC68030.

The parity feature is not implemented on the MVME147-010.

The MVME147 has parity check which operates in one of three user

selectable modes.

In mode 1, no parity checking is performed and the DRAM operates

at maximum speed.

In mode 2, parity checking is performed for all bus masters and the

DRAM operates at maximum speed when the MC68030 is bus

master. When a parity error occurs in mode 2 and the MC68030 is

the local bus master, the bus error signal is not activated during the

current cycle. The bus error is activated during all subsequent

MC68030 DRAM cycles. All other bus masters are notified of parity

errors during the current cycle, consequently their DRAM access

time increases by 1 clock.

In mode 3, parity checking is performed for all bus masters and

parity errors are reported during the current cycle. In this mode, the

DRAM access time is extended by one clock cycle to allow for parity

checking.

MC68030 DRAM Accesses

The MC68030 is the default local bus master, therefore it is the local

bus master as long as no other device requests local bus mastership.

PCC DRAM Accesses

When the PCC needs to transfer data, it requests local bus

mastership from the GCC multiport arbiter. When the PCC has

been granted local bus mastership, it executes one bus cycle and

then releases bus mastership. If a parity error is detected during a

PCC to DRAM read cycle, a bus error is returned to the PCC. 

Functional DescriptWhen the VMEbus map decoder detects an onboard DRAM select,

the VMEchip requests local bus mastership from the GCC

multiport arbiter. When the GCC multiport arbiter has granted

local bus mastership, a DRAM read or write cycle happens and the

VMEchip activates the DTACK* (or BERR* if parity is enabled and

a parity error occurs) signal on the VMEbus.