IC698CPE030嵌入式模块，GE中文PDF说明书在线阅读
这些位对LAN芯片生成的中断级别进行编程。级别0不生成中断。位3当该位为高位时，中断被启用。中断是此位低时禁用。位7当该位为高位时，在以下位置生成LAN端口中断：以位0-2编程的电平。该位是电平敏感的，并且当中断启用和LAN中断激活时激活。当本地发生奇偶校验错误时，设置该位处理器正在访问RAM。
IC698CPE030嵌入式模块通过将1写入它该位通过重置清除。位1该位在通电复位时设置。它被清除给它写一个1。安装MVME147BUG后，其初始化代码清除该位。位设置和清除指令不应用于此控制寄存器。因为中断被写入1到状态位，状态位为1到指示挂起的中断，读-修改-写序列可能清除挂起的中断。这些位编程SCSI端口生成的中断级别。级别0不生成中断。这些位通过重置。位3当该位为高位时，中断被启用。中断是此位低时禁用。该位通过重置清除。位4该位用于控制SCSI总线上的重置信号。什么时候该位较低，SCSI重置信号不由MVME147驱动。当该位高时，SCSI重置由MVME147驱动。该位通过重置清除。位5该位表示SCSI重置信号的状态。当这个位低，则SCSI重置信号未激活。当该位较高时，SCSI重置信号处于活动状态。位6当该位为高位时，将在以下位置生成SCSI重置中断：以位0-2编程的电平。该位是边缘敏感的，并且设置在中断启用和SCSI重置的前沿。写入1或中断时，该位被清除已禁用。清除后，它将保持清除状态，直到下一个中断启用和SCSI重置的前沿。这一位是通过重置清除。位7当该位为高位时，SCSI端口中断在以位0-2编程的电平。该位是位6和的ORSCSI芯片中断。该位通过重置清除。
These bits program the interrupt level the LAN chip generates.
Level 0 does not generate an interrupt.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low.
Bit 7 When this bit is high, a LAN port interrupt is being generated at
the level programmed in bits 0-2. This bit is level sensitive and it
is active when interrupt enable and LAN interrupt are active. This bit is set when a parity error occurs while the local
processor is accessing RAM. This bit is cleared by writing a 1 to
it. This bit is cleared by reset.
Bit 1 This bit is set when a power-up reset occurs. It is cleared by
writing a 1 to it. When the MVME147BUG is installed, its
initialization code clears this bit. Bit set and clear instructions should not be used on this
control register. Because the interrupt is cleared by
writing a 1 to status bit and the status bit is a 1 to
indicate a pending interrupt, the read-modify-write
sequence may clear a pending interrupt. These bits program the interrupt level the SCSI port generates.
Level 0 does not generate an interrupt. These bits are cleared by
reset.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low. This bit is cleared by reset.
Bit 4 This bit is used to control the reset signal on the SCSI bus. When
this bit is low, the SCSI reset signal is not driven by MVME147.
When this bit is high, the SCSI reset is driven by MVME147.
This bit is cleared by reset.
Bit 5 This bit indicates the state of the SCSI reset signal. When this bit
is low, the SCSI reset signal is not active. When this bit is high,
the SCSI reset signal is active.
Bit 6 When this bit is high, a SCSI reset interrupt is being generated at
the level programmed in bits 0-2. This bit is edge sensitive and it
is set on the leading edge of interrupt enable and SCSI reset.
This bit is cleared when a 1 is written to it or when the interrupt
is disabled. When cleared, it remains cleared until the next
leading edge of interrupt enable and SCSI reset. This bit is
cleared by reset.
Bit 7 When this bit is high, a SCSI port interrupt is being generated at
the level programmed in bits 0-2. This bit is the OR of bit 6 and
the SCSI chip interrupt. This bit is cleared by reset.
