VMIVME-7700 350-007700-111000 H燃机卡件

此32位读/写寄存器指向物理DMA传输期间使用的地址和字节计数选择表格模式时。表地址必须为长字对齐，因为位0和1始终为零。如果表地址位0或1集，它们被截断，不会生成错误。这些位不受重置影响。有关表中的详细信息，请参阅第5章住址数据地址寄存器该32位读/写寄存器指向物理地址，其中要传输数据。

VMIVME-7700 350-007700-111000 H燃机卡件数据只能传输到/从板载DRAM或VMEbus内存。这些位不受重置字节计数寄存器该32位读/写寄存器包含一个以位为单位的24位字节计数器0-23，第24-26位为3位功能代码，第31位为链路位。这个字节计数器包含要传输的字节数。这个传输数据时使用功能代码位。当设置为表条目，链路位表示DMA中有更多条目桌子该位在最后一个表条目中被清除。链接位仅为用于表格模式，从不由MC68030设置。这些位是不受重置影响。该16位读/写寄存器保存滴答定时器预加载值。当计数器达到$FFFF时，加载该值，如果启用中断后，生成中断。运行时，计数器每6.25微秒递增一次。以下内容应使用等式确定a的计数器值（n）时间t的周期性中断，其中t以秒为单位。定时器可编程为每隔一段时间产生中断在6.25微秒到0.4096秒之间。这些位不是受重置影响。定时器1计数器寄存器该16位读取寄存器是滴答计数器的输出。读数为未与计数器更新同步。位设置和清除指令不应用于此中断控制寄存器。因为中断是通过向状态位和状态位写入1清除为1表示挂起的中断，读修改写序列可以清除挂起的中断。

Table Address Register

This 32-bit read/write register points to a table of physical

addresses and byte counts that are used during DMA transfers

when table mode is selected. The table address must be longword

aligned because bits 0 and 1 are always zero. If the table address has

bit 0 or 1 set, they are truncated and no error is generated. These bits

are not affected by reset. Refer to Chapter 5 for details on Table

Address.Data Address Register

This 32-bit read/write register points to the physical address where

data is to be transferred. Data can only be transferred to/from

onboard DRAM or VMEbus memory. These bits are not affected by

resetByte Count Register

This 32-bit read/write register contains a 24-bit byte counter in bits

0-23, a 3-bit function code in bits 24-26, and a link bit in bit 31. The

byte counter contains the number of bytes to be transferred. The

function code bits are used when data is transferred. When set in a

table entry, the link bit indicates there are more entries in the DMA

table. This bit is cleared in the last table entry. The link bit is only

used in table mode and is never set by the MC68030. These bits are

not affected by reset.This 16-bit read/write register holds the tick timer preload value.

When the counter reaches $FFFF, it is loaded with this value and if

interrupts are enabled, an interrupt is generated. When running,

the counter is incremented every 6.25 microseconds. The following

equation should be used to determine the counter value (n) for a

periodic interrupt of time t where t is in seconds. The timer may be programmed to generate interrupts at intervals

between 6.25 microseconds and 0.4096 seconds. These bits are not

affected by reset.

Timer 1 Counter Register

This 16-bit read register is the output of the tick counter. Reads are

not synchronized with counter updates.Bit set and clear instructions should not be used on this

interrupt control register. Because an interrupt is

cleared by writing a 1 to the status bit and the status bit

is a 1 to indicate a pending interrupt, the read-modifywrite sequence may clear a pending interrupt.