DEIF TAC-311DG电流变送器,TAC-311DG使用数据

内存选项以下内存选项可用于不同版本的MVME172LX板。DRAM选项MVME172LX提供以下DRAM选项：4MB，8MB或16MB共享DRAM，在夹层上具有可编程奇偶校验模块上的4MB、8MB、16MB、32MB和64MB ECC DRAM夹层板。非ECC内存的DRAM架构对于4MB或8MB是非交叉的，对于16MB是交叉的。奇偶校验保护当检测到奇偶校验错误时，通过中断或总线异常启用。

DEIF TAC-311DG电流变送器DRAM性能在DRAM内存部分中指定MVME172 VME中MC2chip编程模型中的控制器嵌入式控制器程序员参考指南。DRAM映射解码器可以编程以适应不同的夹层板的基址和尺寸。机载DRAM是通过本地总线重置禁用，并且必须在DRAM之前编程可以访问。请参阅中的MC2chip和MCECC说明MVME172 VME嵌入式控制器程序员参考指南有关详细的编程信息。大多数DRAM设备需要一定数量的访问周期，然后才能执行DRAM完全可以运行。通常，该要求由板载刷新电路和正常DRAM初始化。然而软件应确保至少10个初始化周期对每个RAM组执行。SRAM选项MVME172LX提供128KB的32位宽板载静态RAM在单个非交错架构中，具有板载电池备份。这个SRAM阵列没有奇偶校验保护。车载SRAM和夹层的电池备份功能SRAM由电子营销EM1275设备（或等效），支持一次和二次电源。在如果主板电源出现故障，EM1275将检查电源并切换到电压较高的电源。如果备用电源的电压低于两伏，则EM1275阻止第二个存储周期；这允许软件提供早期警告以避免数据丢失。因为第二次访问可能被阻止在电源故障期间，软件应在依靠数据。MVME172LX提供跳线（在J14上），允许任何一种电源将EM1275的电源连接到VMEbus+5V STDBY引脚或至车载电池的一个电池。例如，主系统备份电源可能是连接到VMEbus+5V STDBY引脚和辅助电源可能是车载电池。如果系统源如果出现故障或板从机箱中卸下，板载电池接管。

Memory Options

The following memory options are available on the different versions of

MVME172LX boards.

DRAM Options

The MVME172LX offers the following DRAM options: either 4MB,

8MB, or 16MB shared DRAM with programmable parity on a mezzanine

module, or 4MB, 8MB, 16MB, 32MB, and 64MB ECC DRAM on a

mezzanine board. The DRAM architecture for non-ECC memory is noninterleaved for 4MB or 8MB and interleaved for 16MB. Parity protection

is enabled with interrupts or bus exception when a parity error is detected.

DRAM performance is specified in the section on the DRAM Memory

Controller in the MC2chip Programming Model in the MVME172 VME

Embedded Controller Programmer’s Reference Guide.

The DRAM map decoder may be programmed to accommodate different

base address(es) and sizes of mezzanine boards. The onboard DRAM is

disabled by a local bus reset and must be programmed before the DRAM

may be accessed. Refer to the MC2chip and MCECC descriptions in the

MVME172 VME Embedded Controller Programmer’s Reference Guide

for detailed programming information.Most DRAM devices require a certain number of access cycles before the

DRAMs are fully operational. Normally this requirement is met by the

onboard refresh circuitry and normal DRAM initialization. However,

software should insure a minimum of 10 initialization cycles are

performed to each bank of RAM.

SRAM Options

The MVME172LX provides 128KB of 32-bit-wide onboard static RAM

in a single non-interleaved architecture with onboard battery backup. The

SRAM arrays are not parity protected.

The battery backup function for the onboard SRAM and the mezzanine

SRAM is provided by an Electro Marketing EM1275 device (or

equivalent) that supports primary and secondary power sources. In the

event of a main board power failure, the EM1275 checks power sources

and switches to the source with the higher voltage.If the voltage of the backup source is lower than two volts, the EM1275

blocks the second memory cycle; this allows software to provide an early

warning to avoid data loss. Because the second access may be blocked

during a power failure, software should do at least two accesses before

relying on the data.

The MVME172LX provides jumpers (on J14) that allow either power

source of the EM1275 to be connected to the VMEbus +5V STDBY pin or