WOODWARD 5501-467数字调节器，5501-467使用区域

MVME162提供1MB、4MB和8MB DRAM选项。DRAM架构对于1MB是非交织的，对于4MB和8MB是交织的。当发生以下情况时，可以在中断或总线异常的情况下启用奇偶校验保护：检测到奇偶校验错误。DRAM性能在DRAM内存控制器在MCchip编程模型中的应用MVME162嵌入式控制器程序员参考指南。DRAM地图解码器可以编程以适应不同的基础夹层板的地址和尺寸。车载DRAM已禁用通过本地总线重置，并且必须在DRAM可以已访问。

WOODWARD 5501-467数字调节器请参阅MVME162嵌入式中的MCchip说明详细编程信息的控制器程序员参考指南。大多数DRAM设备在DRAM之前需要一定数量的访问周期完全可操作。通常，车载刷新可以满足此要求电路和正常DRAM初始化。然而，软件应该确保对每个RAM组执行至少10个初始化周期。电池备份RAM和时钟MVME162上使用了MK48T08 RAM和时钟芯片。这个芯片提供时钟、振荡器、晶体、电源故障检测、内存写保护、8KB RAM和一个28针封装中的电池。时钟以BCD 24小时格式提供秒、分钟、小时、天、日期、月份和年份总体安排28、29（闰年）和30天月的修正为自动生成。时钟不会产生中断。虽然MK48T08是一个8位设备，由MCchip提供的接口支持对MK48T08的8位、16位和32位访问。请参阅MCchip说明第3章和MK48T08数据表中的详细编程和电池寿命信息。VMEbus接口和VMEchip2可选的VMEchip2提供本地总线到VMEbus和VMEbus到本地总线接口。VMEchip2还可以提供VMEbus系统控制器功能。参考MVME162嵌入式控制器程序员的有关详细编程信息的参考指南。参考MVME162嵌入式控制器引脚分配支持信息手册VMEbus背板连接器P1和P2。注意，未使用VMEchip2中的中止开关逻辑。GPI输入不使用位于$FFF40088位7-0的VMEchip2。这个中止开关中断集成在位置处的MCchip ASIC中GPI输入在位置处集成到MCchip ASIC中$FFF4202C，位23-16。输入/输出接口MVME162为许多系统应用提供板载输入/输出。输入/输出功能包括串行端口、工业包（IP）接口和可选LAN以太网收发器和SCSI大容量存储设备的接口

Onboard DRAM

The MVME162 offers a 1MB, a 4MB, and an 8MB DRAM option. The DRAM

architecture is non-interleaved for 1MB and interleaved for 4MB and 8MB.

Parity protection can be enabled with interrupts or bus exception when a

parity error is detected. DRAM performance is specified in the section on the

DRAM Memory Controller in the MCchip Programming Model in the

MVME162 Embedded Controller Programmer’s Reference Guide.

The DRAM map decoder can be programmed to accommodate different base

address(es) and sizes of mezzanine boards. The onboard DRAM is disabled

by a local bus reset and must be programmed before the DRAM can be

accessed. Refer to the MCchip description in the MVME162 Embedded

Controller Programmer’s Reference Guide for detailed programming information.

Most DRAM devices require some number of access cycles before the DRAMs

are fully operational. Normally this requirement is met by the onboard refresh

circuitry and normal DRAM initialization. However, software should insure

that a minimum of 10 initialization cycles are performed to each bank of RAM.Battery Backed Up RAM and Clock

An MK48T08 RAM and clock chip is used on the MVME162. This chip

provides a time-of-day clock, oscillator, crystal, power fail detection, memory

write protection, 8KB of RAM, and a battery in one 28-pin package. The clock

provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour

format. Corrections for 28-, 29- (leap year), and 30-day months are

automatically made. No interrupts are generated by the clock. Although the

MK48T08 is an 8- bit device, the interface furnished by the MCchip supports

8-, 16-, and 32-bit accesses to the MK48T08. Refer to the MCchip description

in Chapter 3 and to the MK48T08 data sheet for detailed programming and

battery life information.

VMEbus Interface and VMEchip2

The optional VMEchip2 provides the local-bus-to-VMEbus and VMEbus-tolocal-bus interfaces. The VMEchip2 can also provide the VMEbus system

controller functions. Refer to the MVME162 Embedded Controller Programmer’s

Reference Guide for detailed programming information. Refer to the MVME162

Embedded Controller Support Information manual for the pin assignments of

VMEbus backplane connectors P1 and P2.

Note that the ABORT switch logic in the VMEchip2 is not used. The GPI inputs

to the VMEchip2 which are located at $FFF40088 bits 7-0 are not used. The

ABORT switch interrupt is integrated into the MCchip ASIC at location

$FFF42043. The GPI inputs are integrated into the MCchip ASIC at location

$FFF4202C, bits 23-16.

I/O Interfaces

The MVME162 provides onboard I/O for many system applications. The I/O

functions include serial ports, IndustryPack (IP) interfaces, and optional

interfaces for LAN Ethernet transceivers and SCSI mass storage devices