PDD500A101 3BHE037649R0101控制卡，ABB使用配置说明
该寄存器用于启用VMEchip中断处理程序来响应特定的实用程序中断请求。当中断处理程序检测到中断请求时从一个启用的功能中，它通过请求MC68030启动中断确认循环来响应如果在PCC中设置了主中断启用位。所有的该寄存器中的位通过任何重置进行清除。如本节GCSR编程部分所述第章，GCSR提供两个全局注意力中断位：SIGLP和SIGHP，允许其他VMEbus主机以低优先级（1级）和高优先级中断MC68030优先级（5级）。
PDD500A101 3BHE037649R0101控制卡将SIGLEN控制位设置为1取消掩码SIGLP中断。位2，如本节GCSR编程部分所述第二章，GCSR提供了四个位置监视器。其中两个位置监视器0和1在访问它们配置为监视的VMEbus地址。LM0EN控制位允许软件屏蔽中断当检测到对监控地址的访问时请求通过位置监视器0。本地中断级别如所示表4-6。将LM0EN位设置为1将取消屏蔽中断。位3 VMEchip允许软件对中断处理程序进行编程在结束VMEbus IACK后生成本地中断周期本地中断的级别如表4-6所示。将IACKEN控制位设置为1启用IACK中断。此功能旨在与VMEchip全局中断功能。如果设置了该位，则本地VMEbus IACK时产生中断（至MC68030循环确认中断（参考中断请求本章注册部分）。如本节GCSR编程部分所述第二章，GCSR提供了四个位置监视器。其中两个位置监视器0和1在访问它们配置为监视的VMEbus地址。LM1EN控制位允许软件屏蔽中断当检测到对监控地址的访问时请求通过位置监视器1。本地中断级别如所示表4-6。将LM1EN位设置为1将取消屏蔽中断。位5，如本节GCSR编程部分所述第二章，全球气候变化报告提供了全球高度优先关注中断位SIGHP，允许其他VMEbus主机中断MC68030。显示了本地中断的级别在表4-6中。将SIGNEN控制位设置为1将取消屏蔽SIGHP中断。位6将SFIEN设置为1启用VMEbus SYSFAIL上的低电平线路导致MC68030中断。水平SYSFAIL*中断如表4-6所示。位7 VMEchip允许软件配置VMEbus主机在写投递模式下操作（即，确认MC68030 VMEbus绑定写入周期，在实际在VMEbus上执行）。如果VMEchip遇到VMEbus总线错误，因为它试图完成写操作循环时，VMEchip通过7级中断通知MC68030，如果
设置WPERREN位。
This register is used to enable the VMEchip interrupt
handler to respond to specific utility interrupt requests.
When the interrupt handler detects an interrupt request
from one of the enabled functions, it responds by requesting the MC68030 to initiate an interrupt acknowledge cycle
if the master interrupt enable bit is set in the PCC. All the
bits in this register are cleared by any reset. As described in the Programming the GCSR section in this
chapter, the GCSR provides two global attention interrupt bits:
SIGLP and SIGHP, which allow other VMEbus masters to
interrupt the MC68030 on a low priority (Level 1) and on a high
priority (Level 5). Setting the SIGLEN control bit to 1 unmasks
the SIGLP interrupt.
Bit 2 As described in the Programming the GCSR section in this
chapter, the GCSR provides four location monitors. Two of
them, location monitor 0 and 1, cause a local interrupt when the
VMEbus address they are configured to monitor is accessed.
The LM0EN control bit allows software to mask the interrupt
requested when an access is detected to the address monitored
by location monitor 0. The level of local interrupt is shown in
Table 4-6. Setting the LM0EN bit to 1 unmasks the interrupt.
Bit 3 The VMEchip allows software to program the interrupt handler
to generate a local interrupt after it concludes a VMEbus IACK
cycle. The level of the local interrupt is shown in Table 4-6.
Setting the IACKEN control bit to 1 enables the IACK interrupt.
This function is intended to be coupled with the use of the
VMEchip global interrupt function. If this bit is set, a local
interrupt (to the MC68030) is generated when a VMEbus IACK
cycle acknowledges the interrupt (refer to the Interrupt Request
Register section in this chapter). As described in the Programming the GCSR section in this
chapter, the GCSR provides four location monitors. Two of
them, location monitor 0 and 1, cause a local interrupt when the
VMEbus address they are configured to monitor is accessed.
The LM1EN control bit allows software to mask the interrupt
requested when an access is detected to the address monitored
by location monitor 1. The level of local interrupt is shown in
Table 4-6. Setting the LM1EN bit to 1 unmasks the interrupt.
Bit 5 As described in the Programming the GCSR section in this
chapter, the GCSR provides a global high priority attention
interrupt bit SIGHP which allows other VMEbus masters to
interrupt the MC68030. The level of the local interrupt is shown
in Table 4-6. Setting the SIGHEN control bit to 1 unmasks the
SIGHP interrupt.
Bit 6 Setting SFIEN to 1 enables a low level on the VMEbus SYSFAIL*
line to cause an interrupt to the MC68030. The level of the
SYSFAIL* interrupt is shown in Table 4-6.
Bit 7 The VMEchip allows software to configure the VMEbus master
to operate in a write posted mode (i.e., acknowledge the
MC68030 VMEbus bound write cycle before it has actually been
executed on the VMEbus). If the VMEchip encounters a
VMEbus bus error as it attempts to complete the write posted
cycle, the VMEchip notifies the MC68030 via Level 7 interrupt if
the WPERREN bit is set.
