EMERSON 5X00105G07 PLC模块
计时器控制状态寄存器1（TCSR1）计时器通过位于BAR2地址偏移0x00处的计时器控制状态暂存器1（TCSR 1）进行控制和监控。该寄存器中的位映射如下：每个定时器都有一个独立选择的时钟源，该时钟源由“定时器x时钟选择”字段中的位模式选择，如下所示：通过将“1”写入适当的“定时器x启用”字段，可以独立启用每个定时器。类似地，通过将“1”写入适当的“timer x IRQ Enable”字段，可以独立启用每个计时器产生的中断。如果中断由计时器产生，则可以通过读取“计时器x引起的IRQ”字段来确定中断源。如果字段设置为“1”，则相应的计时器导致中断。请注意，多个计时器可能会导致一次中断。因此，必须读取所有计时器的状态，以确保识别所有中断源。
Timer Control Status Register 1 (TCSR1)
The timers are controlled and monitored via the Timer Control Status Register 1
(TCSR1) located at offset 0x00 from the address in BAR2. The mapping of the bits in
this register are as follows:Each timer has an independently selectable clock source which is selected by the bit
pattern in the “Timer x Clock Select” field as follows:Each timer can be independently enabled by writing a “1” to the appropriate “Timer x
Enable” field. Similarly, the generation of interrupts by each timer can be
independently enabled by writing a “1” to the appropriate “Timer x IRQ Enable”
field.
If an interrupt is generated by a timer, the source of the interrupt may be determined
by reading the “Timer x Caused IRQ” fields. If the field is set to “1”, then the
respective timer caused the interrupt. Note that multiple timers can cause a single
interrupt. Therefore, the status of all timers must be read to ensure that all interrupt
sources are recognized.
