EPRO PR9376010-011轴位移探头
对于多功能设备，所有功能都可以使用相同的INTx#线，或者每个功能都可以有自己的（最多四个功能），或者它们的任意组合。单个函数永远不能在多条INTx#线上生成中断请求。从PIC通过BIOS定义的线路接受VME中断。BIOS根据哪个系统需要使用中断线来定义要使用的中断线。PCI设备中断图基于PCI总线的外部设备包括PMC站点、以太网控制器和PCI到VME桥。默认BIOS将这些外部设备映射到ICH2的PCI中断请求（PIRQx）线路。该映射如第47页图2-1所示，定义见表2-5。无法修改每个设备上的设备PCI中断线（INTA到INTD）。PCI到VME桥具有通过PCI SERR#线生成非屏蔽中断（NMI）的能力。表2-6描述了NMI使用的寄存器位。SERR中断通过逻辑路由回CPU上的NMI输入线。CPU读取NMI状态控制寄存器以确定NMI源（位设置为1）
For a
multifunction device, all functions may use the same INTx# line, or each may have its
own (up to a maximum of four functions), or any combination thereof. A single
function can never generate an interrupt request on more than one INTx# line.The slave PIC accepts the VME interrupts through lines that are defined by the BIOS.
The BIOS defines which interrupt line to utilize depending on which system requires
the use of the line.
PCI Device Interrupt Map
The PCI bus-based external devices include the PMC sites, Ethernet controller and the
PCI-to-VME bridge. The default BIOS maps these external devices to the PCI
Interrupt Request (PIRQx) lines of the ICH2. This mapping is illustrated in Figure 2-1
on page 47 and is defined in Table 2-5.
The device PCI interrupt lines (INTA through INTD) that are present on each device
cannot be modified.The PCI-to-VME Bridge has the capability of generating a Non-Maskable Interrupt
(NMI) via the PCI SERR# line. Table 2-6 describes the register bits that are used by the
NMI. The SERR interrupt is routed through logic back to the NMI input line on the
CPU. The CPU reads the NMI Status Control register to determine the NMI source
(bits set to 1)
