ABB 70BT01c HESG447024R1处理器板
单个函数不能在多条INTx#线上生成中断请求。从PCI通过BIOS定义的线路接受VMEbus中断。BIOS根据哪个系统需要使用中断线来定义要使用的中断线。PCI到VME桥具有通过PCI SERR#线生成非屏蔽中断（NMI）的能力。表3-5描述了NMI使用的寄存器位。SERR中断通过特定逻辑路由回CPU上的NMI输入线。CPU读取NMI状态控制寄存器以确定NMI源（位设置为1）。在NMI中断例程处理中断后，软件通过将相应的启用/禁用位设置为1来清除NMI状态位。NMI启用和实时时钟寄存器可以屏蔽NMI信号并禁用/启用所有NMI源。
A single function can not generate an interrupt request on more than one INTx# line. The slave PCI accepts the VMEbus interrupts through lines that are defined by the BIOS. The BIOS defines which interrupt line to utilize depending on which system requires the use of the line. The PCI-to-VME Bridge has the capability of generating a Non-Maskable Interrupt (NMI) via the PCI SERR# line. Table 3-5 describes the register bits that are used by the NMI. The SERR interrupt is routed through certain logic back to the NMI input line on the CPU. The CPU reads the NMI Status Control register to determine the NMI source (bits set to 1). After the NMI interrupt routine processes the interrupt, software clears the NMI status bits by setting the corresponding enable/disable bit to 1. The NMI Enable and Real-Time Clock register can mask the NMI signal and disable/enable all NMI sources.
