GVC700AE01机械设备卡件
本地总线内存映射本地总线内存映像由传输类型（TT）信号划分为不同的地址空间。本地资源响应正常访问和中断确认码。正常地址范围响应正常地址范围的设备的内存映射如下表所示。正常地址范围由本地总线上的传输类型（TT）信号定义。在控制器上，传输类型0、1和2定义正常地址范围。表1-4是从$00000000到$FFFFFFFF的整个映射。地图的许多区域是用户可编程的，表中显示了建议的用途。缓存抑制功能可在MC68xx040 MMU中编程。板载I/O空间必须标记为缓存禁止并在其页表中序列化。表1-5进一步定义了本地I/O设备的映射。内存映射http://www.mcg.mot.com/literature1-31 1表1-5。本地总线存储器映射地址范围设备访问的端口宽度大小软件缓存抑制注释板上的可编程DRAM D32 4MB-16MB N 2可编程SRAM D32 128KB-2MB N 2可编程序VMEbus A3说明1注释1。重置启用内存映射的这个空间的解码器，以便它将解码地址空间$FF800000-$FF9FFFFF和$00000000-$003FFFFF。在启用DRAM之前，必须在MC2芯片中禁用0处的解码。DRAM通过位于地址$FFF42048，位24的DRAM控制寄存器启用。PROM/Flash在低地址空间被禁用，PROM控制寄存器位于地址$FFF42040，位20。2.该区域可由用户编程。DRAM和SRAM解码器在MC2芯片中编程，本地到VMEbus解码器在VMEchip2中编程，IP存储器空间在IP2芯片中。3.尺寸近似。4.缓存抑制取决于映射区域中的设备。5.PROM和Flash的大小由MC2芯片ASIC从8位专用总线到32位MPU本地总线确定。由于某些条目的设备大小小于分配的内存映射大小，因此这些条目的设备内容会重复。如果安装了跳线GPI3，则可以访问闪存设备。如果未安装GPI3，则可访问PROM。6.闪存和PROM的大小由MC2芯片ASIC从8位专用总线到32位MPU本地总线确定。由于某些条目的设备大小小于分配的内存映射大小，因此这些条目的设备内容会重复。如果安装了跳线GPI3，则可访问PROM。如果未安装GPI3，则访问闪存设备。7.除非可编程解码器之一被初始化以解码该空间，否则这些区域不被解码。如果它们未被解码，则对该地址范围的访问将生成本地总线超时。必须启用本地总线计时器。下表重点介绍本地I/O设备
Local Bus Memory Map The local bus memory map is split into different address spaces by the transfer type (TT) signals. The local resources respond to the normal access and interrupt acknowledge codes. Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables. The normal address range is defined by the Transfer Type (TT) signals on the local bus. On the controller, Transfer Types 0, 1, and 2 define the normal address range. Table 1-4 is the entire map from $00000000 to $FFFFFFFF. Many areas of the map are userprogrammable, and suggested uses are shown in the table. The cache inhibit function is programmable in the MC68xx040 MMU. The onboard I/O space must be marked cache inhibit and serialized in its page table. Table 1-5 further defines the map for the local I/O devices. Memory Maps http://www.mcg.mot.com/literature 1-31 1 Table 1-5. Local Bus Memory Map Address Range Devices Accessed Port Width Size Software Cache Inhibit Note(s) Programmable DRAM on board D32 4MB-16MB N 2 Programmable SRAM D32 128KB-2MB N 2 Programmable VMEbus A3 Description 1 Notes 1. Reset enables the decoder for this space of the memory map so that it will decode address spaces $FF800000 - $FF9FFFFF and $00000000 - $003FFFFF. The decode at 0 must be disabled in the MC2 chip before DRAM is enabled. DRAM is enabled with the DRAM Control Register at address $FFF42048, bit 24. PROM/Flash is disabled at the low address space with PROM Control Register at address $FFF42040, bit 20. 2. This area is user-programmable. The DRAM and SRAM decoder is programmed in the MC2 chip, the local-to-VMEbus decoders are programmed in the VMEchip2, and the IP memory space is programmed in the IP2 chip. 3. Size is approximate. 4. Cache inhibit depends on devices in area mapped. 5. The PROM and Flash are sized by the MC2 chip ASIC from an 8- bit private bus to the 32-bit MPU local bus. Because the device size is less than the allocated memory map size for some entries, the device contents repeat for those entries. If jumper GPI3 is installed, the flash device is accessed. If GPI3 is not installed, the PROM is accessed. 6. The Flash and PROM are sized by the MC2 chip ASIC from an 8- bit private bus to the 32-bit MPU local bus. Because the device size is less than the allocated memory map size for some entries, the device contents repeat for those entries. If jumper GPI3 is installed, the PROM is accessed. If GPI3 is not installed, the flash device is accessed. 7. These areas are not decoded unless one of the programmable decoders are initialized to decode this space. If they are not decoded, an access to this address range will generate a local bus timeout. The local bus timer must be enabled. The following table focuses on the Local I/O Devices
