GVC703AE01 3BHL00386P0101处理器卡件
或者当存储器阵列大小为16MB并且DRAM技术为每个设备16Mbits时）奇偶校验和奇偶校验异常动作也是可编程的。DRAM阵列大小和设备大小在DRAM空间大小寄存器中初始化。EPROM/闪存周期时间EPROM/闪光周期时间可编程为3至10个总线时钟/字节（4字节=12至40）。（实际循环时间可能会根据设备速度而变化。）数据传输为32位宽。请参阅《MVME162FX嵌入式控制器程序员参考指南》。表1-3。DRAM性能时钟预算操作条件4,2,2,2非交织，读取，25 MHz 4,1,1,1交织，读取25 MHz 3,2,2,2写入，25 MHz 5,3,3,3非交织，读，32 MHz 5,2,2,2交织，读取32 MHz 4,2,2,3写入，32 MHz 1-28计算机组文献中心网站板级硬件描述1 SCSI传输MVME162FX嵌入式控制器包括带DMA控制器的SCSI大容量存储总线接口。SCSI DMA控制器使用FIFO缓冲器将8位SCSI总线连接到32位本地总线。FIFO缓冲器允许SCSI DMA控制器以四个长字脉冲串的形式将数据有效地传输到本地总线。这减少了SCSI设备对本地总线的使用。请参阅《MVME162FX嵌入式控制器程序员参考指南》中的MC2芯片编程模型。DMA控制器的传输速率为44MB/秒，32 MHz，奇偶校验关闭，DRAM和读周期交错。假设SCSI总线上的连续传输速率为5MB/sec，则来自SCSI总线的传输将使用12%的本地总线带宽。LAN DMA传输MVME162FX嵌入式控制器包括一个带DMA控制器的LAN接口。LAN DMA控制器使用FIFO缓冲器将串行LAN总线连接到32位本地总线。FIFO缓冲器允许LAN DMA控制器有效地将数据传输到本地总线。82596CA不执行MC68040兼容的突发周期，因此LAN DMA控制器不使用突发传输。DRAM写入周期需要3个时钟周期（25 MHz）或4个时钟周期，32 MHz，而读取周期需要5个时钟周期。LAN DMA控制器的传输速率在25 MHz或32 MHz时为20MB/sec。假设LAN总线上的连续传输速率为1MB/sec，则来自LAN总线的传输将使用5%的本地总线带宽。连接器MVME162FX嵌入式控制器有两个96位DIN连接器：P1和P2。P1行A、B、C和P2行B提供VMEbus互连。P2行A和C提供到SCSI总线、串行端口和以太网的连接。控制器上的串行端口还连接到前面板上的两个25针DB-25阴连接器J9和J15。四个IP通过四对50针功能描述连接到控制器http://www.mcg.mot.com/literature1-29 1连接器。前面板后面的四个50针连接器用于与IP信号的外部连接。内存芯片夹层板插入两个40针连接器。远程状态和控制远程状态和控制器连接器J4是一个位于控制器前面板后面的20针连接器。它为系统设计者提供了访问关键指示器和重置功能的灵活性。当控制器封装在机箱中且前面板不可见时，此连接器允许将RESET（重置）、ABORT（中止）和LED（发光二极管）功能扩展到系统的控制面板，使其可见。或者，这允许系统设计者构建一个RESET/ABORT/LED面板，该面板可以位于远离控制器的位置。表1-4。J4引脚分配1 P5VF LANLED 2 3 P12VLED SCSILED 4 5 VMELED无连接6 7 RUNLED STSLED 8 9 FAILSTAT无连接10 11 SCONLED ABORTSW 12 13 RESETSW GND 14 15 GND GPI1 16 17 GPI2 GPI3 18 19无连接GND 20 1-30计算机组文献中心网站板级硬件描述1内存映射内存映射有两种观点：❏ 本地总线主控器查看的所有资源的映射（本地总线内存映射）。❏ VMEbus Masters查看的机载资源映射（VMEbus内存映射）。下表中描述的内存和I/O映射适用于所有本地总线主机。VMEchip2中有一些地址转换功能。这允许同一VMEbus上的多个控制器具有不同的虚拟本地总线映射，如不同VMEbus主机所查看的。
or when the memory array size is 16MB and DRAM technology is 16 Mbits per device.) Parity checking and parity exception action is also programmable. The DRAM array size and device size are initialized in the DRAM Space Size Register. EPROM/Flash Cycle Times The EPROM/flash cycle time is programmable from 3 to 10 bus clocks/byte (4 bytes = 12 to 40). (The actual cycle time may vary depending on the device speed.) The data transfers are 32 bits wide. Refer to the MVME162FX Embedded Controller Programmer’s Reference Guide. Table 1-3. DRAM Performance Clock Budget Operating Conditions 4,2,2,2 Non-interleaved, read, 25 MHz 4,1,1,1 Interleaved, read, 25 MHz 3,2,2,2 Write, 25 MHz 5,3,3,3 Non-interleaved, read, 32 MHz 5,2,2,2 Interleaved, read, 32 MHz 4,2,2,2 Write, 32 MHz 1-28 Computer Group Literature Center Web Site Board Level Hardware Description 1 SCSI Transfers The MVME162FX Embedded Controller includes an SCSI mass storage bus interface with DMA controller. The SCSI DMA controller uses a FIFO buffer to interface the 8-bit SCSI bus to the 32-bit local bus. The FIFO buffer allows the SCSI DMA controller to efficiently transfer data to the local bus in four longword bursts. This reduces local bus usage by the SCSI device. Refer to the MC2chip Programming Model in the MVME162FX Embedded Controller Programmer’s Reference Guide. The transfer rate of the DMA controller is 44MB/sec at 32 MHz with parity off and interleaved DRAM and read cycles. Assuming a continuous transfer rate of 5MB/sec on the SCSI bus, 12% of the local bus bandwidth is used by transfers from the SCSI bus. LAN DMA Transfers The MVME162FX Embedded Controller includes a LAN interface with DMA controller. The LAN DMA controller uses a FIFO buffer to interface the serial LAN bus to the 32-bit local bus. The FIFO buffer allows the LAN DMA controller to efficiently transfer data to the local bus. The 82596CA does not execute MC68040 compatible burst cycles, therefore the LAN DMA controller does not use burst transfers. DRAM write cycles require 3 clock cycles at 25 MHz or 4 clock cycles at 32 MHz, and read cycles require 5 clock cycles. The transfer rate of the LAN DMA controller is 20MB/sec at 25 MHz or 32 MHz. Assuming a continuous transfer rate of 1MB/sec on the LAN bus, 5% of the local bus bandwidth is used by transfers from the LAN bus. Connectors The MVME162FX Embedded Controller has two 96-position DIN connectors: P1 and P2. P1 rows A, B, C, and P2 row B provide the VMEbus interconnection. P2 rows A and C provide the connection to the SCSI bus, serial ports, and Ethernet. The serial ports on the controller are also connected to two 25-pin DB-25 female connectors J9 and J15 on the front panel. The four IPs connect to the controller by four pairs of 50-pin Functional Description http://www.mcg.mot.com/literature 1-29 1 connectors. Four 50-pin connectors behind the front panel are for external connections to IP signals. The memory chip mezzanine board is plugged into two 40-pin connectors. Remote Status and Control The remote status and control connector, J4, is a 20-pin connector located behind the front panel of the controller. It provides system designers with flexibility in accessing critical indicator and reset functions. When the controller is enclosed in a chassis and the front panel is not visible, this connector allows the RESET, ABORT, and LED functions to be extended to the control panel of the system, where they are visible. Alternatively, this allows a system designer to construct a RESET/ABORT/LED panel that can be located remotely from the controller. Table 1-4. J4 Pin Assignments 1 P5VF LANLED 2 3 P12VLED SCSILED 4 5 VMELED No connection 6 7 RUNLED STSLED 8 9 FAILSTAT No connection 10 11 SCONLED ABORTSW 12 13 RESETSW GND 14 15 GND GPI1 16 17 GPI2 GPI3 18 19 No connection GND 20 1-30 Computer Group Literature Center Web Site Board Level Hardware Description 1 Memory Maps There are two points of view for memory maps: ❏ The mapping of all resources as viewed by local bus masters (local bus memory map). ❏ The mapping of onboard resources as viewed by VMEbus Masters (VMEbus memory map). The memory and I/O maps which are described in the following tables are correct for all local bus masters. There is some address translation capability in the VMEchip2. This allows multiple controllers on the same VMEbus with different virtual local bus maps as viewed by different VMEbus masters.
