GVC750BE101 3BHE009681R0101工控自动化卡件
DRAM架构对于4MB和8MB是非交错的，而16MB架构是交错的。4MB DRAM选件完全位于控制器的基板上；8MB和16MB选项在夹层模块上包括4MB或12MB。内存没有奇偶校验保护。如果基板上填充了4MB，那么兼容的mezzanies是从4开始的。（即，夹层地址映射从4MB开始。）因此，在4MB基板上，夹层上的内存似乎与基板上的内存相邻。软件可以通过检查偏移地址$25处的寄存器的第七位（第23位）来确定基板上有多少内存。该位在MC2芯片初始化时由硬件状态机设置。《MVME162FX嵌入式控制器程序员参考指南》中MC2芯片编程模型中的DRAM内存控制器部分规定了内存性能。下表定义了用于控制器的基板和夹层内存填充选项的组合。夹层MB基板MB可用DRAM交错MC2芯片大小（@寄存器偏移$25）0 4 4 N 100 4（存储体2）4 8 N 101 12（存储2、3和4）4 16 Y 111功能描述http://www.mcg.mot.com/literature1-15 1 SRAM选项MVME162FX嵌入式控制器的设计包括512KB SRAM选项。SRAM架构是单非交织的。其性能在《MVME162FX嵌入式控制器程序员参考指南》中MC2芯片编程模型中的SRAM内存控制器一节中进行了规定。当主电源断开时，电池向SRAM提供VCC。电池保护的最坏情况是200天。SRAM阵列没有奇偶校验保护。控制器的SRAM电池备份功能由Dallas DS1210S提供。DS1210S支持主电源和辅助电源。当主板电源故障时，DS1210S选择具有最高电压的电源。如果一个源发生故障，DS1210S将切换到冗余源。每次板通电时，DS1210S都会检查电源，如果备用电源的电压低于2伏，则会阻止第二个存储周期。这允许软件提供预警以避免数据丢失。因为DS1210S可以阻止第二次访问，所以软件在依赖数据之前应该至少进行两次访问。控制器提供跳线（J20上），允许DS1210S的电源连接到VMEbus+5V STDBY引脚或板载电池的一个单元。例如，主要系统备用电源可以是连接到VMEbus+5V STDBY引脚的电池，次要电源可以是板载电池。如果系统电源出现故障或板从机箱中卸下，则板载电池将接管。有关跳线配置，请参阅第2章！警告：为了正确操作SRAM，必须在备用电源选择头（J20）上安装跳线组合。如果其中一个跳线用于选择电池，则必须将电池安装在控制器上。如果DS1210S的输入未连接，SRAM可能发生故障。1-16计算机组文献中心网站板级硬件描述1 SRAM由MC2芯片控制，访问时间可编程。有关更多信息，请参阅《MVME162FX嵌入式控制器程序员参考指南》中的MC2芯片描述。关于电池板载SRAM的电源是带有两个BR1225型锂电池的RAYOVAC FB1225电池。电池采用插座，便于拆卸和更换，并提供了一个小电容器，以便快速更换电池，而不会丢失数据。
The DRAM architecture is non-interleaved for 4MB and 8MB, while the 16MB architecture is interleaved. The 4MB DRAM option is located entirely on the controller’s base board; the 8MB and 16MB options include 4MB or 12MB on a mezzanine module. The memory is not parity protected. If the base board is populated with 4MB, the compatible mezzanines are ones that start at four. (i.e. the mezzanine address map starts at 4MB.) Therefore on 4MB base boards, the memory on the mezzanine appears contiguous to the memory on the base board. The software can determine how much memory is on the base board by examining the seventh bit (bit 23) of the register at offset address $25. This bit is set upon MC2 chip initialization by a hardware state machine. Memory performance is specified in the section on the DRAM Memory Controller in the MC2 chip Programming Model in the MVME162FX Embedded Controller Programmer’s Reference Guide. The following table defines the combinations of base board and mezzanine memory population options used for the controller. Mezzanine MB Base Board MB Available DRAM Interleaved MC2 chip Size (@ register offset $25) 0 4 4 N 100 4 (bank 2) 4 8 N 101 12 (banks 2, 3, and 4) 4 16 Y 111 Functional Description http://www.mcg.mot.com/literature 1-15 1 SRAM Options The MVME162FX Embedded Controller’s design includes a 512KB SRAM option. SRAM architecture is single non-interleaved. Its performance is specified in the section on the SRAM Memory Controller in the MC2 chip Programming Model in the MVME162FX Embedded Controller Programmer’s Reference Guide. A battery supplies VCC to the SRAMs when main power is removed. The worst case elapsed time for battery protection is 200 days. The SRAM arrays are not parity protected. The controller’s SRAM battery backup function is provided by a Dallas DS1210S. The DS1210S supports primary and secondary power sources. When the main board power fails, the DS1210S selects the source with the highest voltage. If one source should fail, the DS1210S switches to the redundant source. Each time the board is powered, the DS1210S checks power sources and if the voltage of the backup sources is less than two volts, the second memory cycle is blocked. This allows software to provide an early warning to avoid data loss. Because the DS1210S may block the second access, the software should do at least two accesses before relying on the data. The controller provides jumpers (on J20) that allow either power source of the DS1210S to be connected to the VMEbus +5V STDBY pin or to one cell of the onboard battery. For example, the primary system backup source may be a battery connected to the VMEbus +5V STDBY pin and the secondary source may be the onboard battery. If the system source should fail or the board is removed from the chassis, the onboard battery takes over. Refer to Chapter 2 for the jumper configurations. ! Caution For proper operation of the SRAM, a jumper combination must be installed on the Backup Power Source Select Header (J20). If one of the jumpers is used to select the battery, the battery must be installed on the controller. The SRAM may malfunction if inputs to the DS1210S are left unconnected. 1-16 Computer Group Literature Center Web Site Board Level Hardware Description 1 The SRAM is controlled by the MC2 chip, and the access time is programmable. Refer to the MC2 chip description in the MVME162FX Embedded Controller Programmer’s Reference Guide for additional information. About the Battery The power source for the onboard SRAM is a RAYOVAC FB1225 battery with two BR1225 type lithium cells. The battery is socketed for easy removal and replacement and a small capacitor is provided to allow the battery to be quickly replaced without data loss.
