IS200ISBBG1A模拟量输入模块
因此，该方程简化为：DATA[（8×（3–Byte_Offset））+7:8×（3-Byte_Offset]注意，这显示了字不变的大端和小端分量之间的关键区别。与小端和字节不变大端组件相比，字不变大端部件使用不同的数据总线位传输字节量。对于使用字不变大尾数的半字和字传输，数据传输方式如下：•最高有效字节传输到传输地址。•递减的有效字节被传送到顺序递增的地址。对于使用字不变大端数的大于一个字的传输，数据被分割成字大小的块：•最低有效字被传输到传输地址。•越来越重要的字被转移到递增的地址。第6-63页表6-1、表6-2和表6-3中的32位数据总线可扩展至更广泛的数据总线实现。传输大小小于数据总线宽度的突发传输对于突发的每个节拍具有不同的活动字节通道。第6-63页的表6-1和表6-2显示了在小端或字节不变大端系统中活动的32位总线上的字节通道。在这两种情况下，活动字节通道相同，但最高有效字节和最低有效字节的位置不同。表6-1 32位小端数据总线的活动字节通道传输大小地址偏移data[31:24]data[23:16]data[15:8]data[7:0]字0活动[MS]活动活动[LS]半字0-活动[MS]活动[LS]半字2活动[MS]-活动[LS]-字节0-活动字节1-活动字节2-活动字节3活动/-6数据总线6.2 Endianness ARM IHI 0033B。b版权所有ARM有限公司或其附属公司。保留所有权利。6-63 ID102715非机密表6-3显示了32位总线上在字不变大端系统中活动的字节通道。6.2.4字节不变性使用字节不变的大端数据结构简化了在单个内存空间中访问混合端数据结构的过程。使用字节不变的大端序和小端序意味着，对于数据结构中的任何多字节元素：•无论数据的端序如何，元素都使用相同的连续内存字节。•端序决定了这些字节在内存中的顺序，这意味着它决定了内存中的第一个字节是元素的MS字节还是LS字节。•任何到给定地址的字节传输都会将同一数据总线导线上的八位数据传递到同一地址位置，而不考虑字节所属的任何数据元素的端序。表6-2活动字节通道te 0 Act数据结构在这种结构中，例如，Count是一个两字节的小端元素，意味着它的最低地址是它的LS字节。字节不变性的使用确保了对有效负载的大端序访问不会损坏小端序元素。数据包目的地
and therefore the equation simplifies to: DATA[(8 × (3 – Byte_Offset)) + 7 : 8 × (3 – Byte_Offset)] Note This shows a key difference between word-invariant big-endian and little-endian components. A word-invariant big-endian component transfers a byte quantity using different data bus bits compared to both little-endian and byte-invariant big-endian components. For halfword and word transfers using word-invariant big-endian, data is transferred such that: • The most significant byte is transferred to the transfer address. • Decreasingly significant bytes are transferred to sequentially incrementing addresses. For transfers larger than a word using word-invariant big-endian, data is split into word size blocks: • The least significant word is transferred to the transfer address. • Increasingly significant words are transferred to incrementing addresses. The 32-bit data bus in Table 6-1, Table 6-2 on page 6-63, and Table 6-3 on page 6-63 can be extended for wider data bus implementations. Burst transfers that have a transfer size less than the width of the data bus have different active byte lanes for each beat of the burst. Table 6-1 and Table 6-2 on page 6-63 show the byte lanes on a 32-bit bus that are active in a little-endian or byteinvariant big-endian system. The active byte lanes are identical in both cases, but the locations of the most significant and least significant bytes differ. Table 6-1 Active byte lanes for a 32-bit little-endian data bus Transfer size Address offset DATA[31:24] DATA[23:16] DATA[15:8] DATA[7:0] Word 0 Active[MS] Active Active Active[LS] Halfword 0 - - Active[MS] Active[LS] Halfword 2 Active[MS] Active[LS] - - Byte 0 - - - Active Byte 1 - - Active - Byte 2 - Active - - Byte 3 Active - - - 6 Data Buses 6.2 Endianness ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 6-63 ID102715 Non-Confidential Table 6-3 shows the byte lanes on a 32-bit bus that are active in a word-invariant big-endian system. 6.2.4 Byte invariance The use of byte-invariant big-endian data structures simplifies accessing a mixed-endian data structure in a single memory space. Using byte-invariant big-endian and little-endian means that, for any multi-byte element in a data structure: • The element uses the same continuous bytes of memory, regardless of the endianness of the data. • The endianness determines the order of those bytes in memory, meaning it determines whether the first byte in memory is the MS byte or the LS byte of the element. • Any byte transfer to a given address passes the eight bits of data on the same data bus wires to the same address location, regardless of the endianness of any data element of which the byte is a part. Table 6-2 Active byte lanes te 0 Act data structure In this structure, for example, Count is a two-byte little-endian element, meaning its lowest address is its LS byte. The use of byte invariance ensures that a big-endian access to the payload does not corrupt the little-endian element. Packet Destinati
