IS200ISBBG2AAB,IS200DSPXH1DBD工控模块卡件
仅包括HPROT[3:0]信令的组件的HPROT[6:0]信令。表3-7提供HPROT[6:0]信令的HPROT[3:0]信令组件的映射扩展内存类型HPROT定义的原始信令映射预期使用HPROT映射到内存类型[3][2][6][4][3][2]0 0不可缓存、不可缓冲强有序0 0 0 0设备nE 0 1不可缓存，可缓冲设备0 0 0 1设备-E 1 0可缓存，不可缓冲的直写1 1 1 0直写、可共享1 1可缓存、可缓冲写回1 1 1写回、可共享3传输3.8内存类型ARM IHI 0033B。b版权所有ARM Limited或其附属公司。保留所有权利。3-49 ID102715非机密当在仅包括HPROT[3:0]的系统中使用支持HPROT[6:0]的组件时，可以删除高阶HPROT位。注意：这种方法会导致写入到不可缓存内存的映射。然而，特别是如果提供附加信息以确定更合适的映射，则可以使用替代方案。3转让3.9安全转让3-50版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 3.9安全传输AHB5定义了Secure_transfers属性。此属性定义接口是否支持安全和非安全传输的概念。如果未定义此属性，则接口不支持安全传输。支持安全传输的接口有一个附加信号HNONSEC。该信号对于非安全传输被断言，对于安全传输被解除断言。HNONSEC是地址相位信号，具有与HADDR相同的有效性约束。在不支持安全传输的组件之间进行接口时，必须小心。注意：此信号被定义为当其被断言时，传输被标识为非安全。这与ARM安全扩展实现中的其他信令一致。ARM IHI 0033B.b版权所有ARM Limited或其附属公司。保留所有权利。4-51 ID102715非机密第4章总线互连本章描述了AHB系统所需的附加互连逻辑。它包含以下部分：•第4-52页的互连。•地址解码见第4-53页。•读取第4-54页的数据和响应多路复用器。4总线互连4.1互连4-52版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 4.1互连互连组件提供系统中主设备和从设备之间的连接。单个主系统只需要使用解码器和多路复用器，如以下章节所述。多主系统需要使用互连，该互连提供仲裁和从不同主设备到适当从设备的信号路由。地址、控制和写入数据信令需要此路由。本说明书中未提供用于多主系统（例如单层或多层互连）的不同方法的进一步细节。有关实现多层AHB Lite互连的更多信息，请参阅多层AHB技术概述（ARM DVI 0045）。4总线互连4.2地址解码ARM IHI 0033B。b版权所有ARM Limited或其附属公司。保留所有权利。4-53 ID102715非机密4.2地址解码地址解码器为总线上的每个从设备提供选择信号HSELx。选择信号是高阶地址信号的组合解码。鼓励简单的地址解码方案以避免复杂的解码逻辑并确保高速操作。当HREADY为HIGH（高）时，从属设备必须仅对HSELx、地址和控制信号进行采样，表明电流传输正在完成。在某些情况下，当HREADY为LOW时，可能会断言HSELx，但在当前传输完成时，所选从机已发生变化。可分配给单个从设备的最小地址空间为1KB
.
HPROT[6:0] signaling for a component that only includes HPROT[3:0] signaling. Table 3-7 Mapping of an HPROT[3:0] signaling component to provide HPROT[6:0] signaling Original Signaling Mapping for extended memory type HPROT Definition Expected use HPROT Maps to memory type [3] [2] [6] [4] [3] [2] 0 0 Non-cacheable, Non-bufferable Strongly ordered 0 0 0 0 Device-nE 0 1 Non-cacheable, Bufferable Device 0 0 0 1 Device-E 1 0 Cacheable, Non-bufferable Write-through 1 1 1 0 Write-through, Shareable 1 1 Cacheable, Bufferable Write-back 1 1 1 1 Write-back, Shareable 3 Transfers 3.8 Memory types ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 3-49 ID102715 Non-Confidential When using components that support HPROT[6:0] in a system that only includes HPROT[3:0] then the higher order HPROT bits can be removed. Note This approach results in the mapping of Write-through to Non-cacheable memory. However, an alternative scheme can be used, in particular, if additional information is provided to determine a more appropriate mapping. 3 Transfers 3.9 Secure transfers 3-50 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 3.9 Secure transfers AHB5 defines the Secure_Transfers property. This property defines whether an interface supports the concept of Secure and Non-secure transfers. If this property is not defined then the interface does not support Secure transfers. An interface that supports Secure transfers has an additional signal, HNONSEC. This signal is asserted for a Non-secure transfer and deasserted for a Secure transfer. HNONSEC is an address phase signal and has the same validity constraints as HADDR. Care must be taken when interfacing between components that do not support Secure transfers. Note This signal is defined so that when it is asserted the transfer is identified as Non-secure. This is consistent with other signaling in implementations of the ARM Security Extensions. ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 4-51 ID102715 Non-Confidential Chapter 4 Bus Interconnection This chapter describes the additional interconnect logic required for AHB systems. It contains the following sections: • Interconnect on page 4-52. • Address decoding on page 4-53. • Read data and response multiplexor on page 4-54. 4 Bus Interconnection 4.1 Interconnect 4-52 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 4.1 Interconnect An interconnect component provides the connection between masters and slaves in a system. A single master system only requires the use of a Decoder and Multiplexor, as described in the following sections. A multi-master system requires the use of an interconnect that provides arbitration and the routing of signals from different masters to the appropriate slaves. This routing is required for address, control, and write data signaling. Further details of the different approaches used for multi-master systems, such as single layer or multi-layer interconnects, are not provided within this specification. See Multi-layer AHB Technical Overview (ARM DVI 0045) for more information about implementing a multi-layer AHB-Lite interconnect. 4 Bus Interconnection 4.2 Address decoding ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 4-53 ID102715 Non-Confidential 4.2 Address decoding An address decoder provides a select signal, HSELx, for each slave on the bus. The select signal is a combinatorial decode of the high-order address signals. Simple address decoding schemes are encouraged to avoid complex decode logic and to ensure high-speed operation. A slave must only sample the HSELx, address, and control signals when HREADY is HIGH, indicating that the current transfer is completing. Under certain circumstances it is possible that HSELx is asserted when HREADY is LOW, but the selected slave has changed by the time the current transfer completes. The minimum address space that can be allocated to a single slave is 1KB, and the start and
