IS200ISBDG1A工控卡件,DCS卡件
表现投机。•写入操作不能合并。•从同一主设备到同一从设备的所有读写传输必须保持有序。•不得更改HSIZE指示的传输大小。•允许将传输脉冲串分成若干较小的脉冲串。然而，原始突发中NONSEQ和SEQ转移的总数必须与产生的较小突发中NONSEQ和SEQ转移的总数相同。•HPROT允许的唯一更改是将Bufferabe转换为Non-bufferable。此外，对于设备nE：•必须从最终目的地获得写入响应。此外，对于Device-E：•可从中间点获得写入响应。•在发出写入响应时，所有其他主机都必须能够观察到写入传输。•写传输必须及时到达最终目的地。3.8.5正常内存要求对于所有正常内存，即正常不可缓存内存、直写和回写，所需的行为是：•读取可能是推测性的。•读取可以获取比所需更多的数据。•可以合并写入。•HBURST和HSIZE所示的传输特性可以改变。•从同一主机到重叠地址的读写传输必须保持有序。•对于可共享交易，只有当所有其他主控器都可以看到传输时，才能给出响应。此外，对于普通不可缓存内存：•写入传输必须及时在最终目的地可见。注意：没有机制确定写入传输何时到达其最终目的地。•读取数据必须从以下位置获取：-最终目的地。-正在进行到其最终目的地的写入传输。•如果读取数据是从写入传输中获得的：-必须从最新版本的写入中获得。-不得缓存数据以供以后读取。•读取时不得缓存获取的数据以供以后使用。3转让3.8内存类型3-48版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715注意：对于普通非可缓存存储器，读取数据可以从仍在向其最终目的地进行的写入传输中获得，这与同时传播到最终目的地的读取和写入传输无法区分。以这种方式返回的读取数据并不表示写入传输在最终目的地可见。此外，对于直写：•可以从中间缓存或缓冲区获得写响应。•读取数据可以缓存在中间缓存或缓冲区中。•读写传输需要缓存查找。•写入事务必须及时在最终目的地可见。注意：没有机制来确定写入事务何时在最终目的地可见。此外，对于回写：•可以从中间缓存或缓冲区获得写响应。•读取数据可以缓存在中间缓存或缓冲区中。•读写传输需要缓存查找。•写入事务不需要在最终目的地可见。3.8.6分配属性直写和回写传输包括分配属性HPROT[5]：•在断言时，出于性能原因，本规范建议在缓存中分配此传输。•当取消断言时，出于性能原因，本规范建议不在缓存中分配此传输。3.8.7遗留问题表3-7显示了本规范建议提供的映射
erformed speculatively. • Writes must not be merged. • All read and write transfers from the same master to the same slave must remain ordered. • The size of the transfer, as indicated by HSIZE, must not be changed. • A burst of transfers is permitted to be broken into a number of smaller bursts. However, the total number of NONSEQ and SEQ transfers in the original burst must be the same as the total number of NONSEQ and SEQ transfers in the resultant smaller bursts. • The only change permitted to HPROT is to convert a transfer from Bufferabe to Non-bufferable. Additionally, for Device-nE: • Write response must be obtained from the final destination. Additionally, for Device-E: • The write response can be obtained from an intermediate point. • Write transfers must be observable to all other masters at the point that a write response is given. • Write transfers must arrive at the final destination in a timely manner. 3.8.5 Normal memory requirements For all Normal memory, that is, Normal Non-cacheable memory, Write-through, and Write-back, the required behavior is: • Reads can be speculative. • Reads can fetch more data than required. • Writes can be merged. • The characteristics of the transfer, as indicated by HBURST and HSIZE can be changed. • Read and write transfers from the same master to addresses that overlap must remain ordered. • For Shareable transactions the response must only be given when the transfer is visible to all other masters. Additionally, for Normal Non-cacheable memory: • Write transfers must be made visible at the final destination in a timely manner. Note There is no mechanism to determine when a write transfer has reached its final destination. • Read data must be obtained either from: — The final destination. — A write transfer that is progressing to its final destination. • If read data is obtained from a write transfer: — It must be obtained from the most recent version of the write. — The data must not be cached to service a later read. • Reads must not cache the data obtained for later use. 3 Transfers 3.8 Memory types 3-48 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 Note For a Normal Non-cacheable Memory, read data can be obtained from a write transfer that is still progressing to its final destination, this is indistinguishable from the read and write transfers propagating to arrive at the final destination at the same time. Read data returned in this manner does not indicate that the write transfer is visible at the final destination. Additionally, for Write-through: • The write response can be obtained from an intermediate cache or buffer. • Read data can be cached in an intermediate cache or buffer. • A cache lookup is required for read and write transfers. • Write transactions must be made visible at the final destination in a timely manner. Note There is no mechanism to determine when a write transaction is visible at the final destination. Additionally, for Write-back: • The write response can be obtained from an intermediate cache or buffer. • Read data can be cached in an intermediate cache or buffer. • A cache lookup is required for read and write transfers. • Write transactions are not required to be made visible at the final destination. 3.8.6 Allocate attribute Write-through and Write-back transfers include an Allocate attribute, HPROT[5]: • When asserted this specification recommends, for performance reasons, that this transfer is allocated in the cache. • When deasserted this specification recommends, for performance reasons, that this transfer is not allocated in the cache. 3.8.7 Legacy Considerations Table 3-7 shows the mapping that this specification recommends to provide
