IS200IVFBG1AAA工控卡件
第3-32页。HPROT[3:0]从保护控制信号提供关于总线访问的附加信息，并指示应如何在系统内处理访问。信号指示传输是操作码获取还是数据访问，以及传输是特权模式访问还是用户模式访问。参见第3-44页的保护控制。HPROT[6:4]从HPROT信号的3位扩展，添加扩展内存类型。如果AHB5 Extended_Memory_Types属性为True，则支持此信号扩展。请参阅第3-45页的内存类型。HSIZE[2:0]从表示传输的大小，通常为字节、半字或字。该协议允许最大1024位的更大传输大小。请参见第3-33页的传输大小。HNONSEC从站和解码器表示当前传输是非安全传输或安全传输。如果AHB5 Secure_Transfers属性为True，则支持此信号。请参阅第3-50页的安全传输。HEXCL独占访问监视器独占传输。指示传输是独占访问序列的一部分。如果AHB5 Exclusive_Transfers属性为True，则支持此信号。参见第8-72页的独占访问信令。HMASTER[3:0]独占访问监视器和从属主机标识符。如果主线程具有多个支持独占的线程，则由主线程生成。通过互连进行修改，以确保每个主机都具有唯一标识。如果AHB5 Exclusive_Transfers属性为True，则支持此信号。参见第8-72页的独占访问信令。2信号说明2.2主信号2-22版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 HTRANS[1:0]从机指示当前传输的传输类型。这可能是：•空闲•忙碌•非顺序•顺序。参见第3-30页的传输类型。HWDATA[31:0]从设备在写入操作期间，写入数据总线将数据从主设备传输到从设备。建议最小数据总线宽度为32位。然而，这可以被扩展以实现更高的带宽操作。参见第6-60页的数据总线。HWRITE Slave表示传输方向。当高电平时，该信号表示写传输，当低电平时，表示读传输。它具有与地址信号相同的定时，然而，它必须在整个突发传输期间保持恒定。参见第3-28页的基本传输。a、 写入数据总线宽度不限于32位。第6-65页上的数据总线宽度列出了其他允许的数据宽度。表2-2主信号（续）名称目标描述2信号描述2.3从属信号ARM IHI 0033B。b版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。2-23 ID102715非机密2.3从机信号表2-3列出了从机生成的协议信号。表2-3从机信号名称目的地描述HRDATA[31:0]多路复用器在读操作期间，读数据总线将数据从所选从机传输到多路复用器。多路复用器然后将数据传输到主机。建议最小数据总线宽度为32位。然而，这可以被扩展以实现更高的带宽操作。参见第6-60页的数据总线。HREADYOUT多路复用器当为高电平时，HREADYOUT信号表示总线上的传输已完成。该信号可以被驱动为低电平以延长传输。参见第4-54页的读取数据和响应多路复用器。HRESP多路复用器传输响应通过多路复用器后，向主机提供有关传输状态的附加信息。当LOW（低）时，HRESP信号指示传输状态为OKAY（正常）。当HIGH（高）时，HRESP信号指示传输状态为ERROR（错误）。参见第5-56页的从属传输响应。HEXOKAY多路复用器专用好的。表示独占传输的成功或失败。如果AHB5 Exclusive_Transfers属性为True，则支持此信号。参见第8-72页的独占访问信令。a、 读取数据总线宽度不限于32位。第6-65页上的数据总线宽度列出了其他允许的数据宽度。2信号说明2.4解码器信号2-24版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 2.4解码器信号表2-4列出了解码器生成的协议信号。注：通常，解码器还向多路复用器提供HSELx信号，或从HSELx输出的信号/总线，以使多路复用器能够将适当的信号从所选从设备路由到主设备。重要的是，这些附加的多路复用器控制信号被重新定时到数据相位。
page 3-32. HPROT[3:0] Slave The protection control signals provide additional information about a bus access and indicate how an access should be handled within a system. The signals indicate if the transfer is an opcode fetch or data access, and if the transfer is a privileged mode access or a user mode access. See Protection control on page 3-44. HPROT[6:4] Slave The 3-bit extension of the HPROT signal that adds extended memory types. This signal extension is supported if the AHB5 Extended_Memory_Types property is True. See Memory types on page 3-45. HSIZE[2:0] Slave Indicates the size of the transfer, that is typically byte, halfword, or word. The protocol allows for larger transfer sizes up to a maximum of 1024 bits. See Transfer size on page 3-33. HNONSEC Slave and decoder Indicates that the current transfer is either a Non-secure transfer or a Secure transfer. This signal is supported if the AHB5 Secure_Transfers property is True. See Secure transfers on page 3-50. HEXCL Exclusive Access Monitor Exclusive Transfer. Indicates that the transfer is part of an Exclusive access sequence. This signal is supported if the AHB5 Exclusive_Transfers property is True. See Exclusive access signaling on page 8-72. HMASTER[3:0] Exclusive Access Monitor and slave Master identifier. Generated by a master if it has multiple Exclusive capable threads. Modified by an interconnect to ensure each master is uniquely identified. This signal is supported if the AHB5 Exclusive_Transfers property is True. See Exclusive access signaling on page 8-72. 2 Signal Descriptions 2.2 Master signals 2-22 Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 HTRANS[1:0] Slave Indicates the transfer type of the current transfer. This can be: • IDLE • BUSY • NONSEQUENTIAL • SEQUENTIAL. See Transfer types on page 3-30. HWDATA[31:0]a Slave The write data bus transfers data from the master to the slaves during write operations. A minimum data bus width of 32 bits is recommended. However, this can be extended to enable higher bandwidth operation. See Data buses on page 6-60. HWRITE Slave Indicates the transfer direction. When HIGH this signal indicates a write transfer and when LOW a read transfer. It has the same timing as the address signals, however, it must remain constant throughout a burst transfer. See Basic transfers on page 3-28. a. The write data bus width is not restricted to 32 bits. Data bus width on page 6-65 lists the other permitted data widths. Table 2-2 Master signals (continued) Name Destination Description 2 Signal Descriptions 2.3 Slave signals ARM IHI 0033B.b Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. 2-23 ID102715 Non-Confidential 2.3 Slave signals Table 2-3 lists the protocol signals generated by a slave. Table 2-3 Slave signals Name Destination Description HRDATA[31:0]a Multiplexor During read operations, the read data bus transfers data from the selected slave to the multiplexor. The multiplexor then transfers the data to the master. A minimum data bus width of 32 bits is recommended. However, this can be extended to enable higher bandwidth operation. See Data buses on page 6-60. HREADYOUT Multiplexor When HIGH, the HREADYOUT signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer. See Read data and response multiplexor on page 4-54. HRESP Multiplexor The transfer response, after passing through the multiplexor, provides the master with additional information on the status of a transfer. When LOW, the HRESP signal indicates that the transfer status is OKAY. When HIGH, the HRESP signal indicates that the transfer status is ERROR. See Slave transfer responses on page 5-56. HEXOKAY Multiplexor Exclusive Okay. Indicates the success or failure of an Exclusive Transfer. This signal is supported if the AHB5 Exclusive_Transfers property is True. See Exclusive access signaling on page 8-72. a. The read data bus width is not restricted to 32 bits. Data bus width on page 6-65 lists the other permitted data widths. 2 Signal Descriptions 2.4 Decoder signals 2-24 Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 2.4 Decoder signals Table 2-4 lists the protocol signals generated by the decoder. Note Usually the decoder also provides the multiplexor with the HSELx signals, or a signal/bus derived from the HSELx signals, to enable the multiplexor to route the appropriate signals, from the selected slave to the master. It is important that these additional multiplexor control signals are retimed to the data phase.
