3BHL000391P0101模块卡件
定时器1和2为16位宽，
从定时器1和定时器2加载计数寄存器（TMRLCR12）获得其加载计数，该寄存器位于BAR2地址的偏移量0x10处。该寄存器中的位映射如下：当这些字段中的任何一个被写入时（通过单个32位写入或单独的16位写入），各个定时器在定时器时钟的下一个上升沿加载写入的值，而不管定时器是启用还是禁用。此寄存器中存储的值也会在计时器的终端计数（或超时）时自动重新加载。定时器3加载计数寄存器（TMRLCR3）定时器3为32位宽，从定时器3加载计数器寄存器（TMRLCR3）获得其加载计数，该寄存器位于BAR2地址的偏移0x14处。该寄存器中的位映射如下：当写入该字段时，定时器3在定时器时钟的下一个上升沿加载写入值，而不管定时器是启用还是禁用。此寄存器中存储的值也会在计时器的终端计数（或超时）时自动重新加载。字段位读或写定时器2加载计数TMRLCR12[31..16]R/W定时器1加载计数TMRLCR12[15..0]R/W字段位读/写定时器3加载计数TMRRCR3[31..0]R/W 51定时器3定时器4加载计数寄存器（TMRLCR4）定时器4为32位宽，从定时器4加载计数寄存器（TMRLCR4）获得其加载计数，该寄存器位于距BAR2地址偏移0x18处。该寄存器中的位映射如下：当写入该字段时，无论定时器是启用还是禁用，定时器4都会在定时器时钟的下一个上升沿加载写入的值。
计时器的终端计数
此寄存器中存储的值也会在计时器的终端计数（或超时）时自动重新加载。计时器1和2当前计数寄存器（TMRCCR12）计时器1和计时器2的当前计数可通过计时器1和定时器2当前计数计数器（TMRCCR 12）读取，该寄存器位于BAR2地址的偏移量0x20处。该寄存器中的位映射如下：读取任一字段时，当前计数值被锁存并返回。根据WDT控制状态寄存器（CSR2）中“读取锁存选择”位的设置，有两种模式可确定如何锁存计数。有关这两种模式的更多信息，请参阅CSR2寄存器说明。定时器3当前计数寄存器（TMRCCR3）定时器3的当前计数可通过定时器3当前计数器寄存器（TMRC CR3）读取，该寄存器位于距BAR2地址偏移0x24处。该寄存器中的位映射如下：字段位读取或写入定时器4加载计数TMRLCR4[31..0]R/W字段位读取/写入定时器2计数TMRCCR12[31..16]R.O。字段位读取或写入计时器3计数TMRCCR3[31..0]R.O.52 3 VMIVME-7807/VME-7807RC产品手册读取此字段时，当前计数值被锁存并返回。根据WDT控制状态寄存器（CSR2）中“读取锁存选择”位的设置，有两种模式可确定如何锁存计数。有关这两种模式的更多信息，请参阅CSR2寄存器说明。定时器4当前计数寄存器（TMRCCR4）定时器4的当前计数可以通过定时器4当前计数器寄存器（TMRC CR4）读取，该寄存器位于BAR2地址的偏移0x28处。该寄存器中的位映射如下：读取该字段时，当前计数值被锁存并返回。根据WDT控制状态寄存器（CSR2）中“读取锁存选择”位的设置，有两种模式可确定如何锁存计数。有关这两种模式的更多信息，请参阅CSR2寄存器说明。定时器1 IRQ清除（T1IC）定时器1 IRQ清除（T1IC）寄存器用于清除定时器1引起的中断。写入该寄存器（位于BAR2地址偏移0x30处）将清除定时器1的中断。这也可以通过将“0”写入定时器控制状态寄存器（CSR1）的相应“定时器x引起的IRQ”字段来实现。此寄存器仅写，写入的数据不相关。
Timer 1 and 2 are 16 bit wide,
Get its load count from Timer 1 and Timer 2 load count register (TMRLCR12), which is located at offset 0x10 of BAR2 address. The bit mapping in this register is as follows: When any of these fields is written (through a single 32-bit write or a separate 16 bit write), each timer loads the written value on the next rising edge of the timer clock, regardless of whether the timer is enabled or disabled. The value stored in this register is also automatically reloaded when the timer's terminal counts (or times out). Timer 3 load counter register (TMRLCR3) Timer 3 is 32 bits wide, and its load count is obtained from Timer 3 load counter register (TMRLCR3), which is located at the offset 0x14 of BAR2 address. The bit mapping in this register is as follows: When writing this field, Timer 3 loads the write value on the next rising edge of the timer clock, regardless of whether the timer is enabled or disabled. The value stored in this register is also automatically reloaded when the timer's terminal counts (or times out). Field bit read/write timer 2 load count TMRLCR12 [31.16] R/W timer 1 load count TMRLCR12 [15..0] R/W field bit read/write timer 3 load count TMRRCR3 [31.0] R/W 51 timer 3 timer 4 load count register (TMRLCR4) timer 4 is 32 bits wide, and its load count is obtained from timer 4 load count register (TMRLCR4), which is located at 0x18 offset from the BAR2 address. The bit mapping in this register is as follows: When writing this field, whether the timer is enabled or disabled, timer 4 will load the written value at the next rising edge of the timer clock.
Timer terminal count
The value stored in this register is also automatically reloaded when the timer's terminal counts (or times out). Timer 1 and 2 Current Count Registers (TMRCCR12) The current counts of timer 1 and timer 2 can be read through timer 1 and timer 2 current count counters (TMRCCR 12), which are located at offset 0x20 of BAR2 address. The bit mapping in this register is as follows: when reading any field, the current count value is locked and returned. According to the setting of "Read Latch Selection" bit in WDT control status register (CSR2), there are two modes to determine how to latch count. For more information about these two modes, see the CSR2 register description. Timer 3 current count register (TMRCCR3) The current count of timer 3 can be read through timer 3 current counter register (TMRC CR3), which is located at 0x24 offset from BAR2 address. The bit mapping in this register is as follows: field bit read or write timer 4 load count TMRLCR4 [31.0] R/W field bit read/write timer 2 count TMRCCR12 [31.16] R.O. When the field bit reads or writes to the timer 3 to count TMRCCR3 [31.0] R.O.52 3 VMIVME-7807/VME-7807RC product manual reads this field, the current count value is locked and returned. According to the setting of "Read Latch Selection" bit in WDT control status register (CSR2), there are two modes to determine how to latch count. For more information about these two modes, see the CSR2 register description. Timer 4 current count register (TMRCCR4) The current count of timer 4 can be read through timer 4 current counter register (TMRC CR4), which is located at the offset 0x28 of BAR2 address. The bit mapping in this register is as follows: when reading this field, the current count value is locked and returned. According to the setting of "Read Latch Selection" bit in WDT control status register (CSR2), there are two modes to determine how to latch count. For more information about these two modes, see the CSR2 register description. Timer 1 IRQ clear (T1IC) Timer 1 IRQ clear (T1IC) register is used to clear the interrupt caused by timer 1. Writing to this register (at BAR2 address offset 0x30) will clear the interrupt of timer 1. This can also be achieved by writing "0" to the corresponding "IRQ caused by timer x" field of the timer control status register (CSR1). This register is only for writing, and the written data is irrelevant.
