DSTD150 57160001-UH脉冲直流卡件
需求模式
写入一（1）会导致DMA控制器以按需模式运行。在按需模式下，DMA控制器在其DREQ0#输入被断言时传输数据。断言DACK0#以指示当前本地总线传输响应DREQ0#输入。DMA控制器传送L字（32位）的数据。这可能导致8位或16位总线的多次传输。是是0 13 DMA传输的内存写入和失效模式。当设置为1时，PLX 9656对PCI总线执行存储器写入和失效循环。PLX 9656支持8或16 L字的内存写入和失效大小。大小在系统缓存行大小位（PCICLSR[7:0]）中指定。如果指定的大小不是8或16，PLX 9656执行写入传输，而不是内存写入和失效传输。传输必须在缓存线边界开始和结束。是是0 14 DMA EOT#启用。写入一（1）启用EOT#输入引脚。写入零（0）将禁用EOT#输入引脚。是是0 15快速/慢速终止模式选择。写入零（0）将PLX 9656设置为慢速终止模式。因此，在C或J模式下，BLAST#在最后一次数据传输时被断言以终止DMA传输。结果，在M模式下，BDIP#在最近的16字节边界处被取消断言，并停止DMA传输。写入一（1）表示，如果在DMA期间在按需模式下断言EOT#或取消断言DREQ0#，将立即终止DMA传输。在M模式下，写入一（1）表示BDIP#输出被禁用。结果，当EOT#被断言或DREQ#在按需模式下被解除断言时，PLX 9656 DMA传输立即终止。
Demand model
Writing one (1) causes the DMA controller to operate in demand mode. In on-demand mode, the DMA controller transfers data when its DREQ0 # input is asserted. Assert DACK0 # to indicate that the current local bus transmission responds to DREQ0 # input. DMA controller transfers data of L word (32 bits). This may result in multiple transfers of 8-bit or 16 bit buses. Yes is the memory write and failure mode of 0 13 DMA transfer. When set to 1, the PLX 9656 performs a memory write and fail cycle on the PCI bus. The PLX 9656 supports 8 or 16 L word memory writes and invalidate sizes. The size is specified in the system cache row size bit (PCICLSR [7:0]). If the specified size is not 8 or 16, the PLX 9656 performs a write transfer instead of a memory write and a invalidate transfer. The transfer must start and end at the cache line boundary. Yes is 0 14 DMA EOT # enabled. Write one (1) enable EOT # input pin. Writing zero (0) disables the EOT # input pin. Yes is the 0 15 fast/slow termination mode selection. Writing zero (0) sets the PLX 9656 to slow termination mode. Therefore, in C or J mode, BLAST # is asserted at the last data transmission to terminate DMA transmission. As a result, in M mode, BDIP # is deasserted at the nearest 16 byte boundary and DMA transmission is stopped. Writing one (1) means that if EOT # is asserted or DREQ0 # is unasserted in on-demand mode during DMA, DMA transmission will be terminated immediately. In M mode, writing one (1) means BDIP # output is disabled. As a result, when EOT # is asserted or DREQ # is deasserted in on-demand mode, PLX 9656 DMA transmission is immediately terminated.
DMA清除计数模式
当相应的DMA传输完成时，写入一（1）将清除每个分散/聚集描述符中的字节计数。0 17 DMA通道1中断选择。写入一（1）将DMA通道1中断路由到PCI总线中断。写入零（0）将DMA通道1中断路由到本地总线中断。0 18 DAC链负载。当设置为一（1）时，启用描述符加载PCI双地址循环值。否则，它将使用寄存器的内容。0 19 EOT#结束链接。仅用于分散/聚集DMA传输。当EOT#被断言时，值一（1）表示DMA传输结束当前的“散布/聚集”链接，并继续进行剩余的“散布”/“聚集”传输。当EOT#被断言时，零值（0）表示DMA传输结束当前的散射/聚集传输，并且不会继续剩余的散射/收集传输。0 20有效模式启用。零值（0）表示有效位（DMASIZ0[31]）被忽略。值一（1）表示仅当有效位被设置时才处理DMA描述符（DMASIZ0[31]）。如果设置了有效位，则传输计数为零（0），并且描述符不是链中的最后一个描述符。DMA控制器随后移动到链中的下一个描述符。0 21有效停止控制。零值（0）表示如果设置了有效模式启用位（位[20]=1），则DMA链控制器连续轮询有效位设置为零（0）的描述符（无效描述符）。值一（1）表示当检测到值为零（0）的有效位（DMASIZ0[31]=0）时，链控制器停止轮询。在这种情况下，CPU必须通过设置开始位（DMACR0[1]=1）重新启动DMA控制器。暂停设置DMA
DMA Clear Count Mode
When the corresponding DMA transfer is completed, writing one (1) will clear the byte count in each scatter/aggregate descriptor. 0 17 DMA channel 1 interrupt selection. Write one (1) to route the DMA channel 1 interrupt to the PCI bus interrupt. Write zero (0) to route the DMA channel 1 interrupt to the local bus interrupt. 0 18 DAC chain load. When set to one (1), enable the descriptor to load the PCI dual address loop value. Otherwise, it uses the contents of the register. 0 19 EOT # End Link. Only used for decentralized/aggregated DMA transfers. When EOT # is asserted, a value of one (1) indicates that DMA transmission ends the current "scatter/aggregate" link and continues with the remaining "scatter"/"aggregate" transmission. When EOT # is asserted, a zero value (0) indicates that the DMA transmission ends the current scatter/gather transmission, and the remaining scatter/gather transmission will not continue. 0 20 Valid mode is enabled. A zero value (0) indicates that the significant bit (DMASIZ0 [31]) is ignored. A value of one (1) indicates that the DMA descriptor (DMASIZ0 [31]) is processed only when the significand is set. If the significand is set, the transfer count is zero (0), and the descriptor is not the last descriptor in the chain. The DMA controller then moves to the next descriptor in the chain. 0 21 Valid stop control. A zero value (0) indicates that if the valid mode enable bit (bit [20]=1) is set, the DMA chain controller will continuously poll the descriptor (invalid descriptor) whose valid bit is set to zero (0). A value of one (1) indicates that the chain controller stops polling when a significant bit with a value of zero (0) is detected (DMASIZ0 [31]=0). In this case, the CPU must restart the DMA controller by setting the start bit (DMACR0 [1]=1). Pause setting DMA
