5735088-36 供应 PLC/可编程控制系统
通道存储器
DREQ和DACK活动级别和定时，并启用8237 将要传输的数据块的起始地址写入通道存储器地址寄存器（MAR） 将计数（数据块中的字节数）写入通道计数寄存器。编程8237 当外围设备准备好进行数据传输时，它向DRQ发送高信号 当接收到DRQ并且信道被启用时，控制逻辑将HRQ设置为高。 在下一个周期中，MPU放弃总线并向8237发送HLDA信号。 在接收到HLDA信号之后，DMA断言AEN（地址使能）信号为高。 当整个地址A15–A0在地址总线上可用时，DMA将DACK发送到外围DMA执行（主模式） DMA控制器通过断言必要的控制信号来继续数据传输，直到DACK保持为高。 在数据传输结束时，DMA断言EOP（BAR）信号为低。DMA数据传输也可以通过从外部向EOP（BAR）发送低信号来终止。存储器到存储器禁用存储器到存储器启用信道0地址保持禁用信道0地址保留启用如果位0为0控制器启用控制器禁用正常计时压缩计时如果位0是一个固定优先级旋转优先级延迟写入选择扩展写入选择如果位3=1 DREQ SENSE活动高DREQ感测活动低DACK SENSE激活钻头
Channel memory
DREQ and DACK activity levels and timing, and enable 8237 to write the starting address of the data block to be transmitted to the channel memory address register (MAR) to write the count (number of bytes in the data block) to the channel count register. Programming 8237 When the peripheral is ready for data transmission, it sends a high signal to the DRQ When the DRQ is received and the channel is enabled, the control logic sets the HRQ to high. In the next cycle, the MPU gives up the bus and sends the HLDA signal to the 8237. After receiving the HLDA signal, the DMA asserts that the AEN (address enable) signal is high. When the entire address A15 – A0 is available on the address bus, the DMA sends the DACK to the peripheral DMA for execution (main mode) The DMA controller continues data transmission by asserting the necessary control signals until the DACK remains high. At the end of data transmission, DMA asserts that the EOP (BAR) signal is low. DMA data transmission can also be terminated by sending a low signal to the EOP (BAR) from the outside. Memory to memory disable memory to memory enable channel 0 address remain disable channel 0 address remain enable if bit 0 is 0 controller enable controller disable normal timing compression timing if bit 0 is a fixed priority rotation priority delay write select extend write select if bit 3=1 DREQ SENSE active high DREQ sense active low DACK SENSE active bit
