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BASLER A403K工业相机
Camera Link是一种通信链路用于科学和工业领域的视觉应用。Camera Link于2000年由Basler和机器视觉领域的其他领先公司成立。标准Camera Link支持每秒680 MB的最大数据传输速率，具体取决于配置。采集和评估数据的帧抓取器通常用于通过camera Link接口连接相机和PC。Camera Link提供的最重要的好处是：•视觉技术的公认通信标准（摄像机帧抓取器）•简单且标准化的电缆概念•特别适合高数据速率•用于多种类型数据传输的标准化数据协议，例如单/双抽头、8位、10位、RGB、，等•通过帧抓取器通信端口1与摄像机进行串行通信。使用带温度传感器的模拟输入模块时，提供第九通道。在为AI模块定义其他八个热电偶点时，point Builder Instrumentation（点生成器仪表）选项卡的CJ Compensation（CJ补偿）字段需要第九个点（有关更多信息，请参阅第8节）。2安装在个性模块位置的空腔插件（1C31238H01），为模块提供接线示意图标签。通常，此模块类型不需要实际的个性模块。3升高和降低回退输入可以禁用，并用作用户定义的输入点。配置说明包含在套件1C31174G20中。
在第14节中添加以下更改
位0：该位配置模块（写入）或指示模块的配置状态（读取）。“1”表示模块已配置。位1：强制模块进入错误状态，点亮模块的错误指示灯。位2-5：模块未使用。位6-7：保留用于工厂测试，必须始终设置为0。位8：硬件错误。表示以下一项或多项为真：-FPGA在启动时未正确编程。-EE内存校验和不正确-PROM校验和测试失败。-内部内存诊断失败。如果模拟通道正常，则LED亮起。然后，如果HART消息交换正确发生，LED将闪烁100毫秒。如果模拟通道正常，并且模块发送消息且未收到正确响应，则LED将闪烁400毫秒。第22-2页，在第22-2节（操作）第二段（双通道…序列）后添加以下信息：从版本0C开始，RSR固件支持级联PI配置，其中PI 1的输出用作PI 2的目标位置输入。支持级联操作的其他功能是选择直接/间接PI操作的标志，还有一个名为“撤退”的反收尾功能。这些新功能中的一些实际上独立于级联，但所有这些都在本文中详细描述。第22-9页，删除校准模式部分下完全校准项目符号第二段（任意极限…10.0伏）后的所有剩余段落（六）：第22-9.页，添加以下信息代替上述项目中删除的段落：当要求完全校准时，阀门首先行程至0%。在0%时，解调器增益被调整，直到反馈电压接近10伏。此时解调器增益是最大可能的解调器增益。然后阀移动到100%。如果电压大于10伏或超出刻度，解调器增益将降低，并读取电压读数。该读数为100%标定阀。然后，阀门移动至0%，并读取电压读数。该读数为0%校准值。确定0%校准阀后，新值写入EE存储器
Camera Link is a communication link
for visual applications in the fields of science and industry. Camera Link was founded in the year 2000 by Basler and other leading companies in the machine vision arena. Standard Camera Link enables a maximum data transmission rate of 680 MB per second depending on the configuration. Frame grabbers which collect and evaluate the data are usually used to connect the camera and the PC via the Camera Link interface. The most important benefits afforded by Camera Link are: • Accepted communication standard for vision technologies (camera frame grabber) • Simple and standardized cable concept • Particular suitability for high data rates • Standardized data protocol for several types of date transfer, for example single/dual tap, 8 bit, 10 bit, RGB, etc. • Serial communication to the camera via the frame grabber communication port 1 A ninth channel is provided when using the Analog Input module with temperature sensor. This ninth point is needed for the CJ Compensation field of the Point Builder Instrumentation Tab when defining the eight other thermocouple points for the AI module (refer to Section 8) for additional information). 2 Cavity insert (1C31238H01) that fits into the Personality module position providing a wiring schematic label for the module. Typically, there is no actual Personality module required for this module type. 3 Raise and Lower Runback inputs can be disabled and used as user-defined input points. Configuration instructions are included in Kit 1C31174G20.
Add the Following Changes to Section 14
Bit 0: This bit configures the module (write) or indicates the configuration state of module (read). A “1” indicates that the module is configured. Bit 1: Forces the module into error state, illuminating the module’s Error LED. Bits 2-5: Not used by the module. Bits 6-7: Reserved for factory test, must always be set to 0. Bit 8: Hardware Error. Indicates one or more of the following are true: - The FPGA did not program correctly on startup. - The EE memory checksum is incorrect - The PROM checksum test has failed. - Internal memory diagnostic has failed.If the analog channel is healthy, the LED is illuminated. Then, if a HART message exchange occurs correctly, the LED is blinked off for 100 mSec. If the analog channel is healthy, and if the module sends a message and does not receive a correct response, the LED is blinked off for 400 mSec.Page 22-2, Add the following information after the second paragraph (The dual-channel...sequence.) in Section 22-2 (Operation): Starting with revision 0C, RSR firmware supports a cascaded PI configuration in which the output of PI 1 is used as the target position input for PI 2. Additional features to support cascading operation are flags to select direct/indirect PI operation, and an anti-windup feature called “retreat”. Some of these new features are actually independent of cascading, but all are described in detail in this document. Page 22-9, Delete all of the remaining paragraphs (six) after the second paragraph (Arbitrary limits...10.0 volts.) in the Full Calibration bullet under the Calibrate Mode Section: Page 22-9, Add the following information in place of the deleted paragraphs in above item: When full calibration is requested, the valve first travels to 0%. At 0%,demodulator gain is adjusted until the feedback voltage is near 10 volts. The demodulator gain at this point is the maximum possible demodulator gain. Then the valve travels to 100%. If the voltage is greater than 10 volts, or off-scale, demodulator gain is reduced, and a reading of the voltage is taken. This reading is the 100% calibration valve. Then the valve travels to 0% and a voltage reading is taken. This reading is the 0% calibration value. After the 0% calibration valve is determined, the new values are written to EE memory
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