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5X00502G01数字量输入卡件
12-PULSE LOGIC功能块参数（S13/16）。如果两个转换器中的实际电流没有并联下降，并且没有预期下降，那么延迟时间在REV_delay时间结束后开始，以使系统能够自我纠正。在此期间，反转被阻止。延迟时间以倍数定义循环数（参见REV_DELAY）。桥接器反转将独立于另一个转换器的实际电流信号（如果时间已过）。功能是独立于控制模式（6或12脉冲或DCF模式）。此参数必须具有主控形状和从动形状的设置相同。（S21.232中HL较高）FREV_DELAY12-PULSE LOGIC功能块参数（S13/16）。
当电流参考极性反转时，此延迟时间开始。如果电桥反转成功，此延迟时间被重置。如果桥接器反转失败经过该时间后，将显示故障消息F65。
逆转可能失败，因为一个转换器交换了桥接器或转换器交叉交换桥接器其他的东西。最后，两个转换器的电流不会增加桥该延迟时间定义为循环的倍数（参见REV_delay）。功能独立于控制模式（6或12脉冲或DCF模式）。此参数必须在主控形状和从动形状上具有相同的设置，并且必须大于REV_DELAY和REV_GAP加上安全裕度。（S21.232中HL较高）
12-PULSE LOGIC功能块的输入（S13/16）。
指向模拟硬件输入的指针。默认情况下，模拟输入2已连接。
在作为12脉冲主控器工作的转换器上，实际电流信号从SLAVE必须连接到硬件并传输到此输入。
在作为12脉冲SLAVE工作的转换器上，实际电流信号从MASTER必须连接到硬件并传输到此输入。传递到此指针的信号在插头连接器X18:11处输出通过电缆传输的信号与连接的信号相反。这互连可用于故障安全电路。它可以在所有模式下工作。
根据接线图，应进行以下互连：-如果使用无冗余的12脉冲系统（见INHIB_LOGIC）：
-将此输入连接到两个转换器的RDY_ON（10901），主转换器和跟随者
-如果使用12脉冲冗余系统（见BC-LOGIC）：
-将此输入连接到两个转换器的BC_NOT_ZERO（13621），主转换器和追随者
Parameter of 12-PULSE LOGIC-function block (S13/16 ).
If the actual current doesn´t go down in parallel and as expected in both converters this delay time is started when the time of REV_DELAY has elapsed to enable the system to correct itself. During this time the reversal is blocked. The delay time is defined in multiples of cycles (see REV_DELAY). The bridge reversal will be performed independent of the actual current signal of the other converter, if the time has elapsed. The function is independent of the control mode (6- or 12-pulse or DCF mode). This parameter must have the same setting at the Master and the Follower. (higher HL in S21.232)FREV_DELAY Parameter of 12-PULSE LOGIC-function block (S13/16 ). This delay time is started when the polarity of the current reference is inverted. In case the bridge reversal is successful this delay time is reset. In case the bridge reversal failed the fault message F65 is displayed when the time is elapsed. A reversal may fail because only one converter swapped the bridge or the converters swapped bridges crosswise or something else. At the end the current is not increased at both converters with the same bridge. This delay time is defined in multiples of cycles (see REV_DELAY). ). The function is independent of the control mode (6- or 12-pulse or DCF mode). This parameter must have the same setting at the Master and the Follower and must be greater than the sum of REV_DELAY and REV_GAP plus a safety margin. (higher HL in S21.232)
Input of 12-PULSE LOGIC-function block
(S13/16 ). Pointer to an analog hardware input. In default condition the analog input 2 is connected. At converters working as a 12 pulse MASTER the actual current signal taken out of the SLAVE has to be connected to the hardware and transferred to this input. At converters working as a 12 pulse SLAVE the actual current signal taken out of the MASTER has to be connected to the hardware and transferred to this input.The signal passed to this pointer is outputted at Plug Connector X18:11. The logic level of the signal transferred via the cable is inverted compared the one connected to. This interconnection can be used for a fail-safe circuit. It is operative in all modes. Based on the connection diagram this interconnection should be done: - in case a 12 pulse system without redundancy is in use (see INHIB_LOGIC): - connect this input to RDY_ON (10901) at both converters, the Master and the Follower - in case a 12 pulse system with redundancy is in use (see BC-LOGIC): - connect this input to BC_NOT_ZERO (13621) at both converters, the Master and the Follower
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