公司主营产品图展示
产品优势
1：国外专业的供货渠道，具有价格优势
2：产品质量保证，让您售后无忧
3：全国快递包邮
产品详情介绍
Honeywell SPS5710-2-LF工控模块
CRU320现在支持PACSystems RX3i热网络中的255个PROFINET I/O设备备用CPU冗余系统。PROFINET操作使用PROFINET I/O控制器模块IC695PNC001。冗余操作符合PROFINET V2.3S-2型系统冗余。
中描述了HSB CPU冗余系统中的PROFINET I/O操作
以下用户手册：
PACSystems热备CPU冗余用户手册，GFK-2308K
PACSystems RX3i PROFINET IO控制器用户手册，GFK-2571D增加了对IC695RMX228 128 MB反射式内存模块的支持收发器。
增加了读取IC695CMX128、IC695RMX128和IC695MMX128的反射存储器状态位的能力，以及IC695RMX228（反射存储器模块）。解决串行I/O读取字节COMMREQ（4402）始终返回错误的问题发生错误时的代码100Dh，无论错误如何。当CPU首次通电时，RS-485端口（COM 2）与变送器一起通电启用。一旦CPU OK LED亮起，变送器将进入高阻抗状态照亮。由于这需要有限的时间，如果COM 2端口是用于多点通信，其他设备通过wiredOR连接共享同一电缆。如果其中一个设备在CPU通电时正在进行通信上，这些通信有可能中断，直到CPU将RS-485端口进入高阻抗状态。在以前的版本中，CPU允许配置位内存中的COMMREQ状态字非字节对齐边界上的类型。即使给定的引用没有被字节对齐，固件也会在更新状态之前将其调整到下一个最低字节边界位，覆盖对齐边界和指定位置之间的位。
为确保应用程序按预期运行，3.50版要求配置位存储器类型中的COMMREQ状态字将进行字节对齐。例如，如果用户指定的状态位位置为%I3，CPU将状态位位置与%I1对齐。版本3.50固件要求用户指定适当的对齐地址（%I1），以确保所使用的位置适合其应用。请注意，实际参考位置未更改使用的，但现在为用户明确说明。PACSystems CPU接收来自多个系统的在停止和运行模式之间切换的请求不同的来源。这些包括（但不限于）Proficy机器版、HMI、用户以及运行/停止开关。因为模式有许多潜在的来源
更改请求，可以接收新的模式更改请求
而另一个模式更改请求已经正在进行中。发生这种情况时，CPU评估新模式更改的优先级请求正在进行的模式更改。如果新模式更改请求具有与正在进行的优先级相等或更高，CPU将转换到新的模式，而不是正在进行的模式。但是，如果新模式更改请求具有较低的优先级高于正在进行的优先级，新模式请求被丢弃，CPU完成正在进行的模式更改。扫描模式优先级为（从最高到最低优先级）：停止-停止、停止故障、停止和运行。（注意：IO启用/禁用状态不是模式优先级评估的一部分。）例如，CPU已启用运行IO模式，执行服务请求13功能块，将CPU置于停止IO禁用模式。在完成到停止IO禁用的转换之前，运行/停止开关从启用运行IO更改为禁用运行IO。在这种情况下，CPU忽略来自运行/停止开关的新请求进入运行IO禁用模式，因为：已在处理转到停止IO禁用模式的请求，而停止模式具有更高的值优先于运行模式。
The CRU320 now supports 255 PROFINET I/O Devices in a PACSystems RX3i Hot
Standby CPU Redundancy system. PROFINET operation uses the PROFINET I/O
Controller module IC695PNC001. Redundant operation conforms to PROFINET V2.3
Type S-2 System Redundancy.
PROFINET I/O operation in a HSB CPU Redundancy system is described in the
following user manuals:
PACSystems Hot Standby CPU Redundancy User’s Manual, GFK-2308K
PACSystems RX3i PROFINET IO Controller User Manual, GFK-2571D Adds support for IC695RMX228 128 MB Reflective Memory Module with Single Mode
Transceiver.
Adds ability to read reflective memory status bits for IC695CMX128, IC695RMX128,
and IC695RMX228 (reflective memory modules).
Resolves issue of Serial I/O Read Bytes COMMREQ (4402) always returning error
code 100Dh in the event of an error, regardless of the error.When the CPU is first powered on, the RS-485 port (COM 2) powers up with the transmitter
enabled. The transmitter is placed into a high-impedance state once the CPU OK LED is
illuminated. Since that takes a finite amount of time, this could be an issue if the COM 2 port is
being used in multi-drop communications, and other devices share the same cable via wiredOR connections. If one of those devices is actively communicating when the CPU is powered
up, there is a potential for those communications to be disrupted until the CPU puts the
RS-485 port into high-impedance state.In previous releases, the CPU allowed configuration of COMMREQ Status Words in bit memory
types on a non-byte-aligned boundary. Even though the given reference was not bytealigned, the firmware would adjust it the next-lowest byte boundary before updating status
bits, overwriting the bits between the alignment boundary and specified location.
To ensure that the application operates as expected, release 3.50 requires configuration of
COMMREQ Status Words in bit memory types to be byte-aligned. For example if the user
specified status bit location of %I3, the CPU aligns the status bit location at %I1. Release 3.50
firmware requires the user to specify the appropriate aligned address (%I1) to ensure that the
utilized location is appropriate for their application. Note that the actual reference location
utilized is not changed, but now is explicitly stated for the user.The PACSystems CPU receives requests to change between STOP and RUN mode from many
different sources. These include (but are not limited to) Proficy Machine Edition, HMIs, the user
application, and the RUN/STOP switch. Since there are many potential sources for a mode
change request, it is possible to receive a new mode change request while another is already
in progress. When this occurs, the CPU evaluates the priority of the new mode change
request with the mode change that is in progress. If the new mode change request has an
equal or higher priority than the one already in progress, the CPU transitions to the new
mode instead of the one in progress. If, however, the new mode change request has a lower
priority than the one in progress, the new mode request is discarded and the CPU completes
the mode change that is in progress. The sweep mode priorities are (listed from highest to
lowest priority): STOP HALT, STOP FAULT, STOP, and RUN. (Note: The IO ENABLED/DISABLED
state is not part of the mode priority evaluation.) For example, a CPU is in RUN IO ENABLED
mode and a Service Request 13 function block is executed to place the CPU into STOP IO
DISABLED mode. Before the transition to STOP IO DISABLED is completed, the RUN/STOP
switch is changed from RUN IO ENABLED to RUN IO DISABLED. In this case, the CPU ignores
the new request from the RUN/STOP switch to go to RUN IO DISABLED mode because it is
already processing a request to go to STOP IO DISABLED mode and STOP mode has a higher
priority than RUN mode.
