3BSE019297R1数字量通信框架
每次扫描时，FIP总线控制器自动向PLC提供80位状态数据CPU。总线控制器状态位的起始位置是“状态地址”在总线控制器的硬件配置期间选择。第17–80位包含有关通信信道的状态信息，这些信道可能：
使用建立读/写通道命令建立。存在一个错误位，并且可建立的32个信道中的每个信道的数据传输位。nel 1
79数据传输-通道32
80信道错误-信道32
（状态位17、19、21…79）数据传输位：该位通常设置为0。为脉冲每次传输成功完成时，在连续的PLC扫描中设置为1并返回0。
不要假设当数据传输位变为1时，传输刚刚完成最后一次扫描。数据传输位在时间上与传输不紧密同步。
该位仅表示在前一次读（或写）期间发生了传输时期数据传输位的上升沿，表示传输已完成
成功并不保证下一次传输尚未开始或完成。在里面在建立信道命令的情况下，COMREQ状态字始终为上日期在数据传输位被设置为1之前。
（状态位18、20、22…80）信道错误位：当错误消除时，该位设置为1
在这个频道上检测到
当信道初始建立时，如果在瞬态错误条件消失后，信道恢复正常运行。禅宗
当通道被中止通道命令中止时，nel错误位也设置为0或者当PLC CPU从运行转换到停止时。如果是建立Chan
nel命令，COMREQ状态字始终在信道错误位之前更新设置为1。
如果出现以下情况，程序可以监控该位并重新启动读或写通道命令：
该位指示错误。或者程序可以执行检索详细频道
状态：本章描述如何将通信请求（COMREQ）编程到FIP总线控制器。
COMREQ是90-70系列PLC的程序功能，可用于发送：从CPU到智能模块（如FIP总线控制器）的指令。
FIP总线控制器的COMREQ包括：用于断开活动TCP/IP通信信道。
Each scan, the FIP Bus Controller automatically provides 80 bits of status data to the PLC
CPU. The starting location of the Bus Controller Status bits is the “Status Address”
selected during hardware configuration of the Bus Controller.Bits 17–80 contain status information about communications channels that may be
established using the Establish Read/Write Channel Commands. There is an error bit and
a data transfer bit for each of the 32 channels that can be established.nel 1
...
... 79 Data Transfer - Channel 32
80 Channel Error - Channel 32
(Status Bits 17, 19, 21 ... 79) Data Transfer Bit: This bit is normally set to 0. It is pulsed
to 1 and back to 0 on successive PLC scans each time a transfer completes successfully.
Do not assume that when the Data Transfer bit goes to 1 that a transfer has just completed during
the last scan. The Data Transfer bit is not closely synchronized in time with the transfer.
The bit only indicates that a transfer has occurred during the preceding read (or write)
period. A rising edge on the Data Transfer bit indicating that a transfer has completed
successfully does not guarantee that the next transfer has not begun or completed. In
the case of an Establish Channel command, the COMREQ Status Word is always up
dated before the Data Transfer bit is set to 1.
(Status Bits 18, 20, 22 ... 80) Channel Error Bit: This bit is set to 1 when an error is de
tected on this channel. It is set to 0 when the channel is initially established and if the
channel resumes normal operation after a transient error condition subsides. The Chan
nel Error bit is also set to 0 when the channel is aborted by an Abort Channel command
or when the PLC CPU transitions from RUN to STOP. In the case of an Establish Chan
nel command, the COMREQ Status Word is always updated before the Channel Error bit
is set to 1.
The program can monitor this bit and reinitiate the Read or Write Channel command if
the bit indicates an error. Or the program may execute the Retrieve Detailed Channel
Status This chapter describes how to program communications requests (COMREQs) to a FIP
Bus Controller.
COMREQs are program functions of the Series 90-70 PLC that can be used to send
instructions from the CPU to an intelligent module such as the FIP Bus Controller.
COMREQs for the FIP Bus Controller include:Used to disconnect an active TCP/IP communications channel.
