ICS TRIPLEX T8161B处理器模块
LL_功能块提供超前和滞后功能。只有通过设置TLEAD，块才能用作滞后时间为0.0。滞后功能始终处于活动状态，并具有最小设置为0.01分钟。输入E断言高（1）将启用超前/滞后作用当断言为低（0）时，超前/滞后功能将被旁路，输出将设置为等于输入如果未配置输入E，则块将为启用。LMT_功能块用于限制实际信号。输入A通常会通过功能块，以：输出O1。如果输入超过其中一个限制，则块将输出极限值。如果HI限值设置为低于LO限值，则块将输出高限值。输出状态将：当块处于极限状态时，为高（1）。固件1.30及更高版本中的LN_功能块将输出输入X的自然对数。当输入<=0.0时，输入将被视为大于0.0的最小数字（即1.17…e-38），以及将相应地计算LN。固件1.30及更高版本中的LOG__功能块将输出输入X的底10的对数。当输入<=0.0时，输入将被视为大于0.0的最小数字（即1.17…e-38），并且将根据第m个功能块计算日志。功能块提供通用算术能力。如方框图所示，每个输入具有增益和偏置缩放。然后应用生成的信号到可配置的数学运算（DIV、MUL、ADD和SUB）。
操作A将首先在输入A和上执行B、 接下来将对结果和执行操作B输入C。
MUL或DIV操作的未使用输入将设置为1.0而加法或子运算的值将设置为等于0.0.这些输入的操作将正常运行因此，确保偏置和增益设置为：设置正确。
在DIV操作中，当除数为0.0时，输出将继续最大实数，符号由分子。如果分子为0，输出将为0。MUL_功能块对三个输入信号。任何未使用的输入都将设置为1.0因此对输出没有影响。NND_功能块在三个输入。任何未使用的输入将设置为高（1）。NOR_功能块对三个执行逻辑NOR输入。任何未使用的输入都将设置为低（0）。NOT_功能块对输入执行逻辑NOTA、 任何未使用的输入都将设置为低（0）。
LL_ function blocks provide both lead and lag functions.
The block can function as lag only by setting the TLEAD
time to 0.0. The lag function is always active and has a
minimum setting of 0.01 minutes.
Input E asserted high (1) will enable the Lead/Lag
function. When asserted low (0), the Lead/Lag function
will be bypassed and the output will be set equal to the
input. If input E is not configured, the block will be
enabled. LMT_ function blocks are used to limit a real signal.
Input A will normally pass through the function block to
the output O1. If the input exceeds one of the limits, the
block will output the limit value.
If the HI LIMIT is set lower than the LO LIMIT, the block
will output the high limit value. The output statuses will
be high (1) when the block is in a limit condition. LN_ function blocks, in firmware 1.30 and higher, will output the
natural logarithm of input X. When the input is <= 0.0, the input will
be treated as the smallest number greater than 0.0 (i.e. 1.17....e-38) and
the LN will be computed accordingly. LOG__ function blocks, in firmware 1.30 and higher, will output
the logarithm to the base 10 of input X. When the input is <= 0.0,
the input will be treated as the smallest number greater than 0.0
(i.e. 1.17....e-38) and the LOG will be computed according MTH_ function blocks provide universal arithmetic
capability. As shown in the block diagram, each input has
gain and bias scaling. The resulting signals are then applied
to configurable math operations (DIV, MUL, ADD and
SUB). Operation A will be performed first on inputs A and
B. Operation B will be performed next on the resultant and
input C.
Unused inputs to a MUL or DIV operation will be set to 1.0
and those to an ADD or SUB operation will be set equal to
0.0. The operation of those inputs will function normally
so it is important to insure that the bias and gain settings are
set properly.
In a DIV operation, when a divisor is 0.0 the output will go
to the maximum Real number with the sign determined by
the numerator. If the numerator is 0 the output will be 0. MUL_ function blocks perform arithmetic multiplication on
the three input signals. Any unused input will be set to 1.0
and will therefore have no affect on the output. NND_ function blocks perform a logical NAND on the
three inputs. Any unused input will be set high (1). NOR_ function blocks perform a logical NOR on the three
inputs. Any unused input will be set low (0). NOT_ function blocks perform a logical NOT on input
A. Any unused input will be set low (0).
