3BHE025335R1121使用数据,ABB模块
ICC计数器电路由六个部分组成可编程系统定时控制器（STC）。每个STC为ICC提供四个高速计数器/波形合成接口，提供VMIVME-2540二十四通道数字信号测量和控制。STC计数器可能是单独配置或最多四人一组配置实现各种测量和控制功能。
车载68HC000 CPU配置和管理每个STC直接接口，允许VMEbus主机接口提升到硬件级别以上。订购选项允许VMIVME-2540出厂配置为1，2、4或6个系统定时控制器。
3BHE025335R1121使用数据输入和系统定时控制器的输出缓冲在带有RS-422线路接收器和线路的前面板连接器驾驶员。TTL输入信号兼容性受将RS-422线路接收器的反向输入连接到通过前面板的车载1.4 V参考电压，以及TTL信号传输至同相输入。智能计数器/控制器的用户界面由支持的15 MHz 68HC000 CPU实现64 KB的EPROM固件，128 KB的零等待状态静态RAM，高度集成控制和中断逻辑。VMEbus主机通过以下方式对ICC进行编程：本地内存中的排队函数控制块和发出命令。CPU通过以下方式响应命令：解释功能控制块，配置系统定时控制器，然后确认主机命令配置后，CPU将维护数据本地存储器中测量数据的结构和测量或控制时中断VMEbus主机过程已完成。VMIVME-2540的从VMEbus接口在A32中定位64 Kbyte VMEbus本地内存窗口或具有DIP开关的A24地址空间，具有非特权和/或监督访问。VMEbus主机必须仲裁使用68HC000 CPU进行本地总线访问，因为RAM是共享的。数据访问可以是D32、D24、D16和D08，并且支持未对齐的传输。因为本地CPU从RAM（仲裁器）执行其代码在单一VMEbus数据传输。
The ICC counter circuitry consists of six
programmable System Timing Controllers (STCs). Each
STC provides the ICC with four high-speed
counter/waveform synthesis interfaces, giving the
VMIVME-2540 twenty-four channels of digital
measurement and control. The STC counters may be
configured individually or in groups of up to four to
implement the various measurement and control functions.
The on-board 68HC000 CPU configures and manages each
STC interface directly, allowing the VMEbus host interface
to be elevated above the hardware level. Ordering options
allow the VMIVME-2540 to be factory configured with 1,
2, 4, or 6 System Timing Controllers. The inputs and
outputs of the System Timing Controllers are buffered at the
front panel connectors with RS-422 line receivers and line
drivers. TTL input signal compatibility is supported by
connecting the inverting input of the RS-422 line receiver to
an on-board 1.4 V reference through the front panel, and the
TTL signal to the noninverting input.
The user interface of the Intelligent Counter/Controller
is implemented by a 15 MHz 68HC000 CPU supported by
64 Kbyte of EPROM firmware, 128 Kbyte of
zero-wait-state static RAM, and highly-integrated control
and interrupt logic. The VMEbus host programs the ICC by
queueing function control blocks in local memory and
issuing commands. The CPU responds to the commands by
interpreting the function control blocks, configuring the
system timing controllers, and then acknowledging the host
command. Once configured, the CPU maintains data
structures of measurement data in local memory and
interrupts the VMEbus host when a measurement or control
process is complete.
The slave VMEbus interface of the VMIVME-2540
locates the 64 Kbyte VMEbus local memory window in A32
or A24 address space with DIP switches, with nonprivileged
and/or Supervisory access. The VMEbus host must arbitrate
with the 68HC000 CPU for local bus access since the RAM
is shared. The data accesses may be D32, D24, D16, and
D08, and unaligned transfers are supported. Because the
local CPU executes its code from RAM, the arbiter
relinquishes control of the local resources after a single
VMEbus data transfer.
