8521-TC-SA通用电气卡件,GE使用流程
VMEbus系统重置∗ 信号7.Universe II ASIC（PCI/VME总线）的VMEbus重置源桥架控制器）：系统软件重置和本地软件重置下表显示了受各种类型影响的设备重置次数。有关使用重置的详细信息，请参阅MVME2600/2700系列单板计算机程序员参考指南。Endian问题PowerPC处理器和VMEbus本质上是大端的，而PCI总线本质上是小端的。
8521-TC-SA通用电气卡件以下各节概述MVME2700如何处理Big和little endian操作中的软件和硬件差异。有关endian注意事项的更多详细信息，参考MVME2600/2700系列单板计算机程序员参考指南。处理器/内存域MPC750处理器可以在大端和小端同时工作模式然而，它总是将外部处理器/内存总线视为通过执行地址重排和重新排序，在以little endian模式运行。Raven MPU/PCI中的MPC寄存器总线桥控制器ASIC和Falcon内存控制器芯片组以及DRAM、ROM/Flash和系统寄存器，始终显示为大端词。
Raven ASIC的作用由于PCI总线是little endian，Raven在中执行字节交换从PCI到内存和从处理器到PCI的两个方向在编程以大端运算时保持地址不变处理器和内存子系统的模式。
在little endian模式下，Raven反向重新排列PCIbound访问的地址，并重新排列内存绑定访的地址（来自PCI）。在这种情况下，不进行字节交换。
PCI域PCI总线本质上是小端的。所有直接连接到的设备PCI总线在little endian模式下运行，而与处理器域中的操作。
PCI和SCSISCSI是面向字节流的；中地址最低的字节不管endian模式如何，内存都是第一个要传输的内存。由于Raven ASIC在两个小端都保持地址不变性在大端模式下，SCSI数据不应出现端位问题。Big-endian软件仍然必须考虑字节交换效应然而，当访问PCI/SCSI设备的寄存器时。
The VMEbus SYSRESET∗ signal
7. VMEbus Reset sources from the Universe II ASIC (PCI/VME bus
bridge controller): the System Software reset and Local Software
reset
The following table shows which devices are affected by the various types
of resets. For details on using resets, refer to the MVME2600/2700 Series
Single Board Computer Programmer’s Reference Guide.Endian Issues
The PowerPC processor and the VMEbus are inherently big-endian, while
the PCI bus is inherently little-endian. The following sections summarize
how the MVME2700 handles software and hardware differences in bigand little-endian operations. For further details on endian considerations,
refer to the MVME2600/2700 Series Single Board Computer
Programmer’s Reference Guide.Processor/Memory Domain
The MPC750 processor can operate in both big-endian and little-endian
mode. However, it always treats the external processor/memory bus as
big-endian by performing address rearrangement and reordering when
running in little-endian mode. The MPC registers in the Raven MPU/PCI
bus bridge controller ASIC and the Falcon memory controller chip set, as
well as DRAM, ROM/Flash, and system registers, always appear as
big-endian.
Role of the Raven ASIC
Because the PCI bus is little-endian, the Raven performs byte swapping in
both directions (from PCI to memory and from the processor to PCI) to
maintain address invariance while programmed to operate in big-endian
mode with the processor and the memory subsystem.
In little-endian mode, the Raven reverse-rearranges the address for PCIbound accesses and rearranges the address for memory-bound accesses
(from PCI). In this case, no byte swapping is done.
PCI Domain
The PCI bus is inherently little-endian. All devices connected directly to
the PCI bus operate in little-endian mode, regardless of the mode of
operation in the processor’s domain.
PCI and SCSI
SCSI is byte-stream-oriented; the byte having the lowest address in
memory is the first one to be transferred regardless of the endian mode.
Since the Raven ASIC maintains address invariance in both little-endian
and big-endian modes, no endian issues should arise for SCSI data.
Big-endian software must still take the byte-swapping effect into account
when accessing the registers of the PCI/SCSI device, however.
