IS200TRLYH1BGF燃机通用卡件,GE中文说明
Z8536 CIO设备Z8536 CIO设备通过提供Z85230 ESCC未提供调制解调器控制线路。此外Z8536 CIO设备有三个独立的16位计数器/计时器。这个Z85230接收5 MHz时钟输入。基本模块特征寄存器基本模块功能寄存器包含MVME2603/2604单板计算机的配置。它是一个8位位于ISA I/OSCCP基板上的只读寄存器∗ Z85230 ESCC存在。
IS200TRLYH1BGF燃机通用卡件如果设置，则无车载同步串行支持（不存在ESCC）。如果已清除，安装了Z85230 ESCC，并且有车载支持同步串行通信。PMC2P∗ PMC/PMCIX插槽2存在。如果设置，则没有PCI夹层卡（或PCI扩展设备）安装在PMC插槽2中。如果清除，PMC/PMCIX插槽2包含PCI夹层卡（或PCI扩展设备）。PMC1P∗ PMC插槽1存在。如果设置，则未安装PCI夹层卡在PMC插槽1中。如果清除，PMC插槽1包含PCI夹层卡。VMEP∗ VMEbus存在。如果设置，则没有VMEbus接口。如果清除后，支持VMEbus接口。LANP∗ 存在以太网。如果设置，则不需要以太网收发器接口安装。如果清除，则有车载以太网支持。SCSI存在。如果设置，则没有板载SCSI接口。如果已清除，支持板载SCSI。P2信号多路复用由于P2背板连接器中可用引脚的供应有限在为MVME761输入/输出模式配置的MVME2603/2604型号中，某些信号通过VMEbus连接器P2多路传输，用于额外的输入/输出容量。
受影响的信号是在之间传递的同步输入/输出控制信号基板和MVME761过渡模块。多路复用是对软件完全透明的硬件功能。P2多路复用功能涉及四个信号：MXDO、MXDI、，MXCLK和MXSYNC∗.MXDO是来自主板和MXDI是来自MVME761模块的时间多路复用线路。MXCLK公司是用于MXDO和MXDI数据线的10 MHz位时钟。MXSYNC∗ 是在时隙15（表3-2）由MVME2603/2604基板。MVME761转换模块使用MXSYNC∗ 与基板同步。
MXCLK的10 MHz比特率使用16:1多路复用方案。16个时隙定义和分配如下：
Z8536 CIO Device
The Z8536 CIO device complements the Z85230 ESCC by supplying
modem control lines not provided by the Z85230 ESCC. In addition, the
Z8536 CIO device has three independent 16-bit counters/ timers. The
Z85230 receives a 5 MHz clock input.
Base Module Feature Register
The Base Module Feature Register contains the details of the
MVME2603/2604 single board computer’s configuration. It is an 8-bit
read-only register located on the base board at ISA I/OSCCP∗ Z85230 ESCC present. If set, there is no on-board
synchronous serial support (the ESCC is not present). If
cleared, the Z85230 ESCC is installed and there is on-board
support for synchronous serial communication.
PMC2P∗ PMC/PMCIX slot 2 present. If set, no PCI mezzanine card (or
PCI expansion device) is installed in PMC slot 2. If cleared,
PMC/PMCIX slot 2 contains a PCI mezzanine card (or PCI
expansion device).
PMC1P∗ PMC slot 1 present. If set, no PCI mezzanine card is installed
in PMC slot 1. If cleared, PMC slot 1 contains a PCI
mezzanine card.
VMEP∗ VMEbus present. If set, there is no VMEbus interface. If
cleared, the VMEbus interface is supported.
LANP∗ Ethernet present. If set, no Ethernet transceiver interface is
installed. If cleared, there is on-board Ethernet support.SCSI present. If set, there is no on-board SCSI interface. If
cleared, on-board SCSI is supported.
P2 Signal Multiplexing
Due to the limited supply of available pins in the P2 backplane connectors
of MVME2603/2604 models that are configured for MVME761 I/O mode,
certain signals are multiplexed through VMEbus connector P2 for
additional I/O capacity.
The signals affected are synchronous I/O control signals that pass between
the base board and the MVME761 transition module. The multiplexing is
a hardware function that is entirely transparent to software.
Four signals are involved in the P2 multiplexing function: MXDO, MXDI,
MXCLK, and MXSYNC∗.
MXDO is a time-multiplexed data output line from the main board and
MXDI is a time-multiplexed line from the MVME761 module. MXCLK
is a 10 MHz bit clock for the MXDO and MXDI data lines. MXSYNC∗ is
asserted for one bit time at time slot 15 (Table 3-2) by the
MVME2603/2604 base board. The MVME761 transition module uses
MXSYNC∗ to synchronize with the base board.
A 16-to-1 multiplexing scheme is used with MXCLK’s 10 MHz bit rate.
16 time slots are defined and allocated as follows:
