HIER464920P0001培训教程,ABB模块
❏ 计数器2为上的扬声器输出功能提供音调PIB控制器（扬声器输出信号，可通过电缆连接至通过远程重置连接器连接外部扬声器）。
间隔计时器使用OSC时钟输入作为其时钟源。这个MVME2603/2604使用14.31818 MHz时钟源驱动OSC引脚。16位定时器MVME2603/2604上有四个16位定时器。
HIER464920P0001培训教程PIB控制器提供一个16位定时器；Z8536 CIO设备提供其他三个。有关对这些计时器进行编程的信息，请参阅数据W83C553 PIB控制器和Z8536 CIO设备的图纸，如附录D中列出了相关文件。
串行通信接口MVME2603/2604使用Zilog Z85230 ESCC（增强串行通信控制器）来实现两个串行通信接口，通过P2路由。Z85230支持同步（SDLC/HDLC）和异步协议。这个MVME2603/2604硬件支持的异步串行波特率110B/s至38.4KB/s。
每个接口支持CT、DCD、RTS和DTR控制信号，如以及TxD和RxD发送/接收数据信号，以及TxC/RxC同步时钟信号。因为并非所有调制解调器控制线都可用在Z85230中，Z8536 CIO用于提供缺失的调制解调器线路。PAL设备执行寄存器访问和伪中断的解码在ISA输入/输出空间中确认Z85230和Z8536的周期。这个PIB控制器为Z85230提供DMA支持。
Z85230接收10MHz时钟输入。Z85230提供伪中断确认周期期间的中断向量。向量是根据中断源在Z85230内修改。打断请求级别通过PIB控制器编程。参见Z85230数据表和MVME2603/MVME2604程序员参考指南，均列于附录D相关文件中，以供进一步了解信息
❏ Counter 2 provides the tone for the speaker output function on the PIB controller (the SPEAKER_OUT signal which can be cabled to an external speaker via the remote reset connector). The interval timers use the OSC clock input as their clock source. The MVME2603/2604 drives the OSC pin with a 14.31818 MHz clock source. 16-Bit Timers Four 16-bit timers are available on the MVME2603/2604. The PIB controller supplies one 16-bit timer; the Z8536 CIO device provides the other three. For information on programming these timers, refer to the data sheets for the W83C553 PIB controller and the Z8536 CIO device, as listed in Appendix D, Related Documentation. Serial Communications Interface The MVME2603/2604 uses a Zilog Z85230 ESCC (Enhanced Serial Communications Controller) to implement the two serial communications interfaces, which are routed through P2. The Z85230 supports synchronous (SDLC/HDLC) and asynchronous protocols. The MVME2603/2604 hardware supports asynchronous serial baud rates of 110B/s to 38.4KB/s. Each interface supports the CTS, DCD, RTS, and DTR control signals as well as the TxD and RxD transmit/receive data signals, and TxC/RxC synchronous clock signals. Since not all modem control lines are available in the Z85230, a Z8536 CIO is used to provide the missing modem lines. A PAL device performs decoding of register accesses and pseudo interrupt acknowledge cycles for the Z85230 and the Z8536 in ISA I/O space. The PIB controller supplies DMA support for the Z85230. The Z85230 receives a 10MHz clock input. The Z85230 supplies an interrupt vector during pseudo interrupt acknowledge cycles. The vector is modified within the Z85230 according to the interrupt source. Interrupt request levels are programmed via the PIB controller. Refer to the Z85230 data sheet and to the MVME2603/ MVME2604 Programmer’s Reference Guide, both listed in Appendix D, Related Documentation, for further information.
