LPF240A工控卡件,HITACHI使用过程
网络引导控制模块的“控制”能力需要与将所有必要的模块（功能）放在一起，并对引导进行排序过程引导序列包括两个阶段：第一阶段标记为“地址确定和引导文件选择”，第二阶段标记为“文件传输”。第一阶段将利用RARP/BOOTP功能和第二阶段将利用TFTP能力。网络输入/输出错误代码如果尝试的网络操作失败，197Bug将返回错误代码不成功的多处理器支持MVME197LE双端口RAM功能使共享RAM可用于远程处理器以及本地处理器。
LPF240A工控卡件这可以通过以下方式实现：以下两种方法之一。任何一种方法都可以通过ENV命令作为其远程启动开关方法（参考附录A）。多处理机控制寄存器（MPCR）方法远程处理器可以在本地MVME197LE中启动程序执行双端口RAM，通过使用多处理器发出远程GO命令控制寄存器（MPCR）。MPCR位于3000美元的共享RAM位置从调试器加载它的基址的偏移量，包含两个用于控制处理器之间通信的文字。MPCR内容组织如下：多处理器地址寄存器（MPAR），位于共享RAM中调试器加载它的基址的3004美元偏移量的位置，包含两个字中的第二个字，用于控制处理器之间的通信。MPAR内容指定远程执行的地址如果MPCR包含G或B，则处理器开始。MPAR组织为通电后，调试监视器自检例程初始化RAM，包括用于多处理器支持的内存位置。MPCR在通电时包含$00，表示尚未初始化完成随着初始化的进行，执行路径到达“提示”例程。在发送提示之前，此例程在MPCR指示初始化完成。然后发送提示。如果没有终端连接到端口，则仍会轮询MPCR以查看是否外部处理器需要将控制传递给双端口RAM。如果a终端没有响应，MPCR被轮询用于相同的目的，而正在轮询串行端口以供用户输入。
Network Boot Control Module
The “control” capability of the Network Boot Control Module is needed to tie
together all the necessary modules (capabilities) and to sequence the booting
process. The booting sequence consists of two phases: the first phase is labeled
“address determination and bootfile selection” and the second phase is labeled
“file transfer”. The first phase will utilize the RARP/BOOTP capability and the
second phase will utilize the TFTP capability.
Network I/O Error Codes
197Bug returns an error code if an attempted network operation is
unsuccessful.
Multiprocessor Support
The MVME197LE dual-port RAM feature makes the shared RAM available to
remote processors as well as to the local processor. This can be done by either
of the following two methods. Either method can be enabled/disabled by the
ENV command as its Remote Start Switch Method (refer to Appendix A).
Multiprocessor Control Register (MPCR) Method
A remote processor can initiate program execution in the local MVME197LE
dual-port RAM by issuing a remote GO command using the Multiprocessor
Control Register (MPCR). The MPCR, located at shared RAM location of $3000
offset from the base address the debugger loads it at, contains one of two
words used to control communication between processors. The MPCR
contents are organized as follows:The Multiprocessor Address Register (MPAR), located in shared RAM
location of $3004 offset from the base address the debugger loads it at, contains
the second of two words used to control communication between processors.
The MPAR contents specify the address at which execution for the remote
processor is to begin if the MPCR contains a G or B. The MPAR is organized as
followsAt power up, the debug monitor self-test routines initialize RAM, including
the memory locations used for multi-processor support ($3000 through $3007).
The MPCR contains $00 at power-up, indicating that initialization is not yet
complete. As the initialization proceeds, the execution path comes to the
“prompt” routine. Before sending the prompt, this routine places an R in the
MPCR to indicate that initialization is complete. Then the prompt is sent.
If no terminal is connected to the port, the MPCR is still polled to see whether
an external processor requires control to be passed to the dual-port RAM. If a
terminal does respond, the MPCR is polled for the same purpose while the
serial port is being polled for user input.
